Require exact synchronization between start of DAC DMA and start of ADC DMA

[CactusPete]

Our measurements required an exact time between successive DAC and ADC DMA conversions.  Time measurements are in the microsecond level and we currently have too much variation in timing triggering DMA transfers via software and using a software time delay between DAC and ADC DMA conversions.

We selected STM chips based on HAL to reduce the time to production and therefore are seeking a solution via HAL.  We are using the H753ZI and V chip.  I've been working on trying to use linked timers for over a week, but I believe the HRTIM may be the best option, but is far too complex and would probably takes months to figure out.

Would it be possible to get a simple example of DAC DMA and ADC DMA that are started at N microseconds apart and using a 1000 point buffer each using HAL?

This is really the only issue barring us from moving to production.

Thanks,

Peter

[CactusPete]

My requirement is to start the ADC after the DAC.  Not change the phase - this is your solution and now I know why I did not understand it - it was not what I had asked for.

I need a sampling clock to be feed into both the DAC and ADC.  Same sample time.   But I need this sampling clock to start LATER for the ADC.  This LATER time needs to be up to 1000 x that of the sample time.

This is why setting the PULSE value had no visible effect ... it was such a minor change and within one sample period - not what is needed.  I may have been unclear in my initial description.

I've also seen a post using master/slave, but the person gave up and no solution was found.

So hopefully this help clarify my requirements.

I'm trying with master/slave. Just one slave for the ADC, but the STM HAL and such are so difficult to piece together this may be easier with an AND gate to delay a bloody clock externally for the ADC.  But it should be possible??

If anyone knows how to accomplish this via HAL or other method I'd appreciate any help.

Thanks,

Peter

[TDK]

It is my fault for putting so much effort into a solution where the requirements were not stated clearly. And now I'm frustrated so we're in the same boat.

> Would it be possible to get a simple example of DAC DMA and ADC DMA that are started at N microseconds apart and using a 1000 point buffer each using HAL?

I guess what is missing here is the sample rate, and the value of N. If it's less than 1 sample per N microseconds, my solution works.

> This LATER time needs to be up to 1000 x that of the sample time.

Would have been good to know at the outset. And there are solutions, but I'm out for this one.

[CactusPete]

Don't think that will work due to the max delay being one sampling time.  Actual settings will have a sampling time of 1us and a delay setting from 0 to about 0.14 seconds.  Orders of magnitude different from the sampling time. If I had an external 1 us clock and an AND gate controlled by GPIO I could probably make two clocks with a delay to feed the DAC and ADC DMA jobs that are setup via software, but there must be a way to do this without going to external hardware???

Not measuring phase shifts here - something very different, but require exact timing between DAC and ADC cycles. Also not continuous - need to start an DAC ADC cycle for each reading (processing time in between that is non-trivial and time consuming).

Hope you have another idea to get this to work.

Thanks,

Peter

[CactusPete]

The number of samples will be 2,000 to 8,000 points perhaps a bit higher.

[CactusPete]

Unfortunately the phase shift from TDK does NOT answer anything related to this requirement.  As stated the delay will be potentially 100 x  that of the sampling time of the ADC/DAC.  So please look elsewhere .... no solution here.