Reduce ADC sampling rate

[deckhard]

Hi

The default stm32h7 ADC sampling rate is 50MSps.

how can I reduce it using HAL settings?

something like 50KSps?

Is it possible to do so during run time while the is ADC is already on?

Is there any risk of using the internal ADC at the maximum sample rate? For an application which uses it a lot? Could it wear down the ADC peripheral with time?

Thanks

[TDK]

> The default stm32h7 ADC sampling rate is 50MSps.

Pretty sure that's way higher than possible.

If you have continuous conversions enabled, the ADC will go as fast as it can. Increasing sampling time will slow down the rate. Slowing down the ADC clock will also slow down the sampling rate.

Otherwise, you should set it up to trigger off of a timer, and set the timer to the desired sampling frequency. That's the common approach.

> Is there any risk of using the internal ADC at the maximum sample rate?

There should be no risk to the ADC by running it fast, other than it generating more heat.

[deckhard]

50MSps is the highest for this chip according to datasheet.

I'm not using the continues mode, I'm using the ADC in Polling mode.

If I do a single sample once every 50ms, assuming the ADC clock is at maximum frequency 50Mhz.

How do I lower the sampling rate for 50kSps?

Thanks a a lot!

[TDK]

If you're doing polling mode and sampling every 50ms, then your sample rate is 20 sps, not 50 Msps.
It sounds like you're asking how to adjust the ADC clock. The clock configuration in CubeMX should let you choose from the available clock sources.

[Uwe Bonnes]

Read the datasheet again. 50 MHz is the highest ADC clock resulting in 3.6 Msamples/s at 16 bit with shortest sampling time. Allow longest sampling time (810 clocks) und your are at about 65 kHz sampling frequency.

[deckhard]

Will adjusting the ADC clock/prescaler affect the sample rate? or just the maximum rate possible?

[deckhard]

@Uwe Bonnes​ You're right. I meant 5Msamples/s in 14bit mode.

[deckhard]

I understand that the application determines the sample rate right?

With the ADC setting the highest possible rate which is the limit, am I correct?

If I need a faster rate I can lower the resulotion.

So what lowering the ADC clock affects? the sample rate limit?

[deckhard]

How do I set it up for the longest sampling time 810 clock?

[deckhard]

I see the configuration now - > ADC_SAMPLETIME_2CYCLES_5

So if I program it to 810.5 sample time, I can still safely sample using polling at 20 SMps right?

Can I change the sample time during run time?