STM32F407: Can SPI SD or USB handle 2.4 MB/s (24 kB/10 ms) logging?

[agha]

I write six 32-bit floats to RAM every 10 µs (100 kHz) via DMA. I batch and flush every 10 ms → 1000 samples × 24 B = 24 kB per block → 2.4 MB/s average.
RAM buffers: planning double/triple buffering (48–72 kB) in SRAM1/2 (CCM isn’t DMA-accessible).

SPI SD card path:
• Is ~2.4 MB/s sustained feasible over SPI-mode SD on F407?
• Proven settings welcome: SPI clock, DMA, FatFs multi-block writes, file pre-allocation, 4–32 kB write chunks, f_sync cadence, and buffer size to ride out SD write stalls.
• (I know SDIO 4-bit is safer; I’m asking specifically about SPI-mode viability.)

USB path:
• USB FS (12 Mb/s) can’t sustain 2.4 MB/s payload.
• With USB HS (480 Mb/s + external ULPI PHY) it should be easy: 24 kB every 10 ms is ~4.5% bus.
• Any working configs for CDC vs raw Bulk, 512-B packets, TX FIFO sizing, DMA double-buffering, and host side (WinUSB/libusb/Matlab) readers?

Fallbacks:
• Quantize to Q15 (int16) → 12 kB/10 ms = 1.2 MB/s; FS becomes borderline/possible with careful buffering, or keep floats and reduce sample rate.

Any real-world numbers, scope captures, or code snippets would be greatly appreciated.

[TDK]

For an SD card, if all you're doing is a sequential write, 2.4 MBps should be no problem. Most cards are optimized for sequential writing and won't have random delays like it would with random writes. Exact specs will depend on the memory being used but in general it's a safe bet to say it'll work.

For USB, you'll need a buffer of up to 50 ms or so to accomodate random delays with USB. Longer buffers needed depending on how busy the CPU is and how often the program reads from the buffer. Sustained 40+ Mbps is possible.

[agha]

Thanks for nice answer. On STM32F407VG, I’m planning to use SDIO + DMA. For double-buffering, if I allocate 2×48 KB (≈96 KB) in SRAM1 alone, is that safe enough? (F407VG RAM: SRAM1 = 112 KB, SRAM2 = 16 KB, CCM = 64 KB — DMA cannot access CCM). Alternatively, is it fine to place bufA in SRAM1 and bufB in SRAM2? Also, can I safely put the stack and CPU-only variables (like EKF matrices) into CCM to free up SRAM1 for DMA buffers?

[TDK]

The exact answer will depend on the specs of the memory being used.

Buffers in SRAM1 and/or SRAM2 are basically equivalent here.

Yes, you can put the stack in CCMRAM.