Record/Monitor an SPI Conversation

[John Craven]

I would like to record/monitor a "3rd party" SPI bus conversation.

I have a couple logic analyzers, that work fine on the bench.

But i need longer term recording, and i need to do it in an environment without a PC and as small as i can get.

And i am trying avoid having to record the raw logic transitions, and then decode the SPI later.

I looked at synchronous mode for usart for F4, and if i read thing correctly, they have to act as the master and generate the clk, and can only receive when they are transmitting (and generating the clk). There is no slave mode that uses an external clk signal during receive.

I used SPI peripherals in master mode only. I have briefly look at SPI slave mode.

I am wondering if i could setup 2 x SPI peripherals, as slaves, only connect the RX side, and listen to the 3rd party MISO/MOSI lines.

Thought i would ask the gurus here if that is possible?, am i missing something? or if there is a better way?

[After Forever]

> Thought i would ask the gurus here if that is possible?, am i missing something? or if there is a better way?

Not a guru (: But if I were in your shoes and needed a quick solution I would use something like a Bus Pirate (maybe connected to a Raspberry Pi for recording the sniffed data if your "without a PC" condition holds).

[S.Ma]

https://www.innesys.com/SPI-bus-protocol-analyzer/?pid=101

https://www.totalphase.com/products/beagle-i2cspi/

Not so simple, even if you use 2 SPI as Slave to monitor the MISO and MOSI (STM32 MISO disabled of course) using DMA for max data fill, the max SPI frequency will be probably SYSCLK/4 (if the core works at 100MHz, max SPI Slave will be 25mbps).

And then, where do you store this datalog? uSD card? Datarate? Latency?

[John Craven]

Yes i looked at that option. Its not out of the running. Raspberry is still bigger and more awkward and less robust then i would like to achieve.

[John Craven]

Yes my idea was to disable the slave MISO.

The bus i am looking at is running at 4Mhz. Looking at my bench logic analyzer recordings, there is a consistent 14000 bytes per second on the MOSI/MISO lines.

Ideally it would use DMA to capture the SPI.

Ideally i would toggle buffers, with SDIO DMA recording.

I am comfortable with handling 28kB of SDIO (or even SD/SPI) data per second.

At this point, was just looking for firm "SPI side, no it won't work or isn't possible", so i don't waste a lot of time.

[S.Ma]

For 4MHz, it should be fine.

Just remember that SPI has a shift register (typically 8 or 16 bit), so if the bus is noisy or some malformed missing/extra SCK clocks are seen on the bus, the cell may just report error. So as long as the SPI bus is fairly functional and the purpose is datalogging, it should be doable. Make sure besides SPI all SW and HW peripherals needed to perform the decoding is available.

On the log side, think on how you want to record and manage NSS signal in your log.

[John Craven]

Yes, the next challenge after the raw collection of spi bytes is timestamping the spi frames/packets.

Based on my recordings, the there are about 4400 frames per second.

Almost all the transactions are 2byte reg read/writes. With regular but less frequent 40/48 byte buffer read/writes.

My first thought would to put the CS line to a timer and capture timestamps to a dma buffer.

And use a timer (or another gpio) interrupt on the same CS line, and capture the NDTR of the SPI DMA buffer(s).

[S.Ma]

You can just capture the DMA location on NSS edges, If you also connect NSS to a 32 bit timer channel, you could also capture timestamps with DMA too.

The more HW assisted, the more rugged the solution become.

[John Craven]

Ok, the basic capture is running.

I have two SPI units configure as read only slaves, on the monitored MISO/MOSI, both connected to the monitored NSS.

Both are recording into DMA buffers.

I have half full and complete interrupts, starting UART DMA transmits to USB, of the buffer halves. I will add the SDIO capture later.

I have a 32bit timer with prescaler setup so i have 1us counting. I have input capture so the monitored NSS start of frame/packet time is captured.

I am getting all the raw spi data and frame timestamps.

In the past, i have done GPIO port capture to MEM using DMA, with a timer providing the DMA sampling triggers.

If i configure a MEM to MEM circular transfer, with the source address pointed at the SPI DMA CNDTR, with no source increment, can i use the timer capture event, as timer out trigger that can trigger sampling of the CNDTR DMA capture?