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RC filter before ADC

hanqingze
Associate III

Previously through testing using fast channal, single-ended input can realize less than 1.5M sinusoidal FFT, I want to add RC filter on the input, but I don't know what is the limitation for RC selection? Please help me, the cutoff frequency of the rc filter I designed is around 10M, how should I choose the size? Will this size affect the maximum frequency I can capture? Because I read the table below, but I don't know what it means.

hanqingze_0-1727154534413.png

 

4 REPLIES 4
PGump.1
Senior II

I'm confused - you understand FFT? But you don't understand RC?

 

Kind regards
Pedro

AI = Artificial Intelligence, NI = No Intelligence, RI = Real Intelligence.

I know of course about RC filters, but in RC filters, the choice of R and C values is usually related to the internal design of the MCU, and I'd like to know if there are any special requirements for the STM32H743VI, such as the table I posted above, which seems to limit the sampling speed, but I don't think that's very clear.

PGump.1
Senior II

It maybe that you need to implement the R&D strategy of - "suck-it-and-see"....

 

Kind regards
Pedro

AI = Artificial Intelligence, NI = No Intelligence, RI = Real Intelligence.

@hanqingze wrote:

want to add RC filter on the input, but I don't know what is the limitation for RC selection?


Output impedance of the RC filter is important as the filter is loaded by the ADC.
Input impedance of the RC filter is important as the filter loads the input signal.
Considering the relatively low input impedance of the ADC I would use an active filter instead or a passive filter with an output buffer.

 


@hanqingze wrote:

 Please help me, the cutoff frequency of the rc filter I designed is around 10M, how should I choose the size?


R*C = 1 / (2*pi*f) = 1.59E-8


@hanqingze wrote:

 Because I read the table below, but I don't know what it means.


The higher the output impedance of your source or the higher the desired resolution the longer the sampling capacitor takes to charge up to be within the margin of error of the selected resolution. This means a longer sampling time.
The total conversion time depends on the sampling time and the hold time (which is where the actual conversion takes place).

https://www.st.com/resource/en/application_note/an1636-understanding-and-minimising-adc-conversion-errors-stmicroelectronics.pdf

 

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