2025-07-17 3:43 AM
Hi,
We would like to implement a parity checks on the internal RAM to detect random upsets. I understand some STM devices support this feature and I was trying to find one that supports it. I have searched several datasheets but so far I can't find mention of it.
I found a thread that stated that the STM32F3 has it, but the STM32F4, I don't know if that is true. Do any H5,H7,F7 support this feature? Is this feature still supported in the latest devices?
Regards
Jon
2025-07-17 4:29 AM
Hi @JS6000 ,
Welcome to ST Community!
If your purpose is to explore error detection capabilities, please note that STM32H7 and STM32H5 series support advanced RAM ECC (Error Correction Code) mechanisms for internal SRAM. This feature is configurable for safety and reliability. The article Injecting and handling ECC errors in STM32H7 RAM will be helpful if you want to implement ECC with STM32H7.
Regarding the RAM parity check, it is available on other mainstream or low-power products such as STM32C0, STM32G0, STM32F0, STM32U0, and STM32L4.
-Amel
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2025-07-17 9:02 AM
Thanks Amel,
For the quick reply, that looks to be what we need, but I will read it carefully to see if I have further questions. I had seen some mention of the ECC Memory corrections, but had believed that was for external memory.
-Jon
2025-07-17 11:21 AM - edited 2025-07-17 11:23 AM
Hello @JS6000 ,
See also the AN5342 "How to use error correction code (ECC) management for internal memories protection on STM32 MCUs"
The applicable products: