Question on STM32 DMA FIFO

apiccianoit · ‎2014-02-14

Posted on February 14, 2014 at 18:01

Hi All,

reading the reference manual of the STM32, I have a question related to a transfer peripheral to memory using DMA, direct mode ( no FIFO )

In section 9.3.12, Direct Mode paragraph, i found:

Direct mode

By default, the FIFO

operates

in direct mode (DMDIS bit in the DMA_SxFCR is reset) and

the FIFO threshold level is not used. This mode is useful when the system requires an

immediate and single transfer to or from the memory after each DMA request.

When the DMA is configured in direct mode (FIFO

disabled

), to transfer data in memory-toperipheral mode, the DMA preloads one data from the memory to the internal FIFO to

ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.

To avoid

saturating the FIFO

, itis recommended to configure the corresponding stream with

a high priority.

My question is: even if the FIFO threshold is not used, is the FIFO still active? To say with other words: if the peripheral is sending bytes at a very high speed, it can happen that I lost a byte or the FIFO helps me to store the previous bytes?

Thank you very much,

Antonio

#dma-fifo #fifo #direct-mode #dma

waclawek.jan · ‎2014-02-19

Posted on February 19, 2014 at 16:21

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/DispForm.aspx?ID=38500&RootFolder=%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex%5fmx%5fstm32%2fSTM32F4%20DMA%20streams%20init%20sequence&Source=https%3A%2F%2Fmy%2Est%2Ecom%2Fpublic%2FSTe2ecommunities%2Fmcu%2FLists%2Fcortex%5Fm...

Tesla DeLorean · ‎2014-02-19

Posted on February 19, 2014 at 16:46

The model is STM32F205. With very high speed I mean a peripheral sending bytes very fast. E.g. UART @921600 ( a byte every 10us )

Ok, so not particularly fast compared to a processor running at 120 MHz, I think where it will start having consequences is a 30 MHz or so (ie a significant percentage of available bandwidth), where hard deadlines are difficult to meet with contended buses.

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paolo · ‎2014-05-30

Posted on May 30, 2014 at 12:21

Hi Antonio,

I'm probably facing a very similar problem. Moreover I see that, supposing that DMA perfoms multiple write actions to memory without waiting for a TC interrupt clear, no ''Direct Mode Error'' notification. From Reference Manual: ''Direct mode error: the direct mode error interrupt flag (DMEIFx) can only be set in the

peripheral-to-memory mode while operating in direct mode and when the MINC bit in

the DMA_SxCR register is cleared. This flag is set when a DMA request occurs while

the previous data have not yet been fully transferred into the memory (because the

memory bus was not granted). In this case, the flag indicates that 2 data items were be

transferred successively to the same destination address, which could be an issue if

the destination is not able to manage this situation''.

Have you found a workaround?

Thank you in advance.

Ciao

paolo · ‎2014-05-30