QuadSPI read with data only phase (Indirect mode)

[juan luis ferrando]

Posted on February 14, 2018 at 13:20

Hi all,

I am trying to read from the QuadSPI peripherial but with data only phase removing the rest of the phases (no address, no dummy, no instrucction and no alternate). The problem is that as described in the manual there are to ways to trigger the conversion:

---------------------------

Indirect-read mode (FMODE = 01)

Communication

start

s immediately if:

�A write is performed to INSTRUCTION [7:0] (QUADSPI_CCR), and if no address is required (ADMODE=00).

�A write is performed toADDRESS [31:0] (QUADSPI_AR), and if an address is necessary (ADMODE!=00)

------------------------------------------------------

I have tried both but I cannot actually read any data. For the first one (writting the instructtion of quadspi_CCR register) I have tried the following code:

----------------------

//config:

  sCommand_qspi.InstructionMode   = QSPI_INSTRUCTION_NONE;

  sCommand_qspi.AddressMode       = QSPI_ADDRESS_NONE;  sCommand_qspi.Address           = ((uint32_t)0x0050);  sCommand_qspi.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;  sCommand_qspi.DataMode          = QSPI_DATA_4_LINES;  sCommand_qspi.DummyCycles       = 0;  sCommand_qspi.NbData            = 4;  sCommand_qspi.DdrMode           = QSPI_DDR_MODE_DISABLE;  sCommand_qspi.DdrHoldHalfCycle  = QSPI_DDR_HHC_ANALOG_DELAY;  sCommand_qspi.SIOOMode          = QSPI_SIOO_INST_ONLY_FIRST_CMD;

//set functional mode as Indirect read mode

  MODIFY_REG(hqspi.Instance->CCR, QUADSPI_CCR_FMODE, ((uint32_t)QUADSPI_CCR_FMODE_0));

      /* Start the transfer by writing the address CCR register */

      __IO uint32_t *data_reg = &hqspi->Instance->DR;

          MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_INSTRUCTION, 0x03);          while(hqspi->RxXferCount > 0)

          {            /* Wait until FT or TC flag is set to read received data */            status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, 100);     

       if  (status != HAL_OK)

            {              break;            }            *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;            hqspi->RxXferCount--;          }

-------------------------------

but It actually just send a few cycles to read instruction from memory. The subsequent read data commands are not working and it does not generate the clock pulses to read the samples.

The second option was to wirte the address register as described in the manual, but it does not work for my application since it only seems to work when the address is sent as header (ADMODE!=00) and this is not what I would like to do. In all the functions of HAL driver the reception starts like this:

WRITE_REG(hqspi->Instance->AR, addr_reg);

But as I mentioned before I do not want to include the Address header in my read.

In the manual it clearly states the following:

------------

The QUADSPI communicates with the Flash memory using commands. Each command

can include 5 phases: instruction, address, alternate byte, dummy, data. Any of thesephases can be configured to be skipped, but at least one of the instruction, address,alternate byte, or data phase must be present.

---------------------------------

So apparently data phase only should be possible.

Could you please provide some guidance for this?

BTW, the micro is STM32H743XI (development board)

Many thanks.

Best regards,

Juan Luis

#quadspi

[Andreas Bolsch]

Posted on March 07, 2018 at 23:57

Where is the write to DLR?

[Amel NASRI]

Posted on March 13, 2018 at 17:49

Hi

juanluis.ferrando

‌,

So

apparently data phase only should be possible.

Unfortunately, it is not the case: QuadSPI could not be configured with only data phase activated in indirect read mode.

This is a limitation that we recently found, only for STM32H7x3 devices.

In such case, you can apply the following workaround: enable the dummy phase with at least 2 dummy cycles.

Is it possible for you to apply this workaround? If yes, please confirm if this resolves the issue, or you still facing any problem.

Please note that this limitation will be added in the next revision of STM32H7 errata sheet.

-Amel

[juan luis ferrando]

Posted on April 02, 2018 at 13:08

Hi

st.mcu

,

It does not resolve the issue for me. In my opinion, the QuadSPI communication would be really powerful communicating to 4 external ICs like ADCs in parallel if just the data phase could be received. I know this is not the intention of the QuadSPI interface but you could think about this in the future. I hope you can improve this limitation.

For example, for my application, if 4-8 external high-speed ADCs could be used in parallel with an STM microcrotroller, could replace a FPGA and reduce the complexity of the design.

In any case Many thanks for the response!

[Tesla DeLorean]

Posted on April 02, 2018 at 14:48

Not really a very common/standard use case. People often use CPLD to translate common protocols to assorted different, and user specific, hardware configurations.

Or ask ADC vendors to provide a Quad ADC supporting Quad SPI protocol.

[ribdp]

Hello, 

I noticed that the STm32H5 errata doesn't mention anything about this limitation. However, the CubeFW imposes that limitation through if-checks anyway. 

Is it known whether data phase only or data phase + dummy cycles, are supported in the STM32H563 hardware? Or do you need to compulsorily send at least one of address or instruction?

Any help is appreceiated!

Thanks!