About ribdp

ribdp · 2024-05-21

So the background is essentially this - I am trying to use one of the streams of STM32F4 DMA2 in circular, DBM mode.The DMA stream is being used to move data out of the SPI DR register at regular intervals, as soon as data becomes available at SPI RX...

ribdp · 2024-05-20

In the STM32F469, can the bus arbitration priority (amongst the different bus masters) be changed? From my reading of the Application Notes and the Reference Manuals this doesn't seem to be the case. But I'd like to get a confirmation just the same. ...

ribdp · 2024-03-27

Hello, I'm using the STM32F469NiH6 to try and do a certain number of SPI transactions (let's say 12 bytes) at regular intervals without core intervention, using Timers and DMA. And I have a couple of questions concerning this (I have had a look into ...

ribdp · 2024-06-13

Hello, I noticed that the STm32H5 errata doesn't mention anything about this limitation. However, the CubeFW imposes that limitation through if-checks anyway. Is it known whether data phase only or data phase + dummy cycles, are supported in the STM3...

ribdp · 2024-05-21

Thanks @Danish1 !So, you can register two separate callbacks with HAL - one for M0-complete, and the other for M1-complete. The callback I was referring to, above, is the M0-complete - here I hope to ultimately be able to update the M0AR. There is a ...

ribdp · 2024-05-21

Hi @Danish1 , thanks for the reply!Sorry, should've mentioned I registered a callback using the HAL API, so I'm positive the transfer-complete callback is invoked only when CT=1.To be doubly sure, I also stored the CR register value inside the callba...

ribdp · 2024-03-28

So, I'm planning to setup a DMA stream respond to SPI TXE events, that will put bytes (or half-words) into the DR (data register) of SPI to initiate the transactions autonomously. I also want to have a predetermined delay between two consecutive 12 b...

ribdp · 2024-03-28

Thanks for the reply! @Uwe Bonnes wrote:If you need the 12 bytes surrounded by assert/deassert CSI wouldn't think assert/deassert CS to be too critical to the problem at hand. I am okay with not using the hardware NSS, and instead driving CS as a PWM...

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Re: STM32F4 DMA Address Update penalty with double buffering

Re: STM32F4 Enabling and Disabling SPI using Timer or DMA

Re: STM32F4 Enabling and Disabling SPI using Timer or DMA