PSSI and DMA issue

[Michal Dudka]

Hi,
I am using PSSI on STM32H7R3 to transmit data with DE output signal and RDY input signal (flow control). Incoming clock frequency is 60MHz. Data buffer is located in AHBSRAM1 and have size 4096 bytes. GPDMA feeds PSSI buffer by 32bit access (four bytes at once). Application while loop waits until DMA transfer complete and then restarts transfer again. Most of the time everything works OK, PSSI correctly reacts on RDY signal by "stopping" transmission (repeating data until RDY asserted), DE signal also works correctly except for one moment. When RDY (PSSI input) and DE (PSSI outout) are deasserted at the same time (clock), then PSSI makes "mistake" and retransmit one byte of data two times.

Data in SRAM buffer are OK (checked by debugger)

PSSI Configuration:
DERDYCFG = 0b11 (both DE + RDY signals used)
DMAEN = 1
OUTEN = 1

On following scope traces can be seen, that PSSI transmites "1" before RDY blocks data flow. When reciever is ready to accept data, asserts RDY and PSSI transmitt "1" again. Data consis of alternating 0 and 1, therefore PSSI should never transmit two same data consecutive.

First transmittion after RDY assertLastr transmittion before RDY deassertoverall view

this event happens when program "reload" DMA (tracked by signal on PB8)

while (1)
{
	while(!(LL_DMA_IsActiveFlag_TC(GPDMA1, LL_DMA_CHANNEL_0))){} // wait until DMA transfer complete
	LL_GPIO_SetOutputPin(GPIOB, LL_GPIO_PIN_8); // indicate moment when DMA is reloaded
	cnt++;
	if(cnt >= 16){
		cnt = 0;
	}
	LL_DMA_ClearFlag_TC(GPDMA1, LL_DMA_CHANNEL_0);
	LL_DMA_SetBlkDataLength(GPDMA1, LL_DMA_CHANNEL_0,BLOCK_SIZE);
	LL_DMA_SetSrcAddress(GPDMA1, LL_DMA_CHANNEL_0, DMA_SRC_ADDRESS);
	LL_DMA_EnableChannel(GPDMA1, LL_DMA_CHANNEL_0);
	LL_GPIO_ResetOutputPin(GPIOB, LL_GPIO_PIN_8); // indicate moment when DMA is reloaded
}

But when i add some delay into "DMA reload" routine, problem dissapears. Following scope trace show that situation:
with delay, it is ok

but then another error appears somewhere else in the data instead. For now I am not able to locate them exactly to rule out that it is a problem in the receiver. Even so, the problem described above is enough to make the transmission unreliable.

Does anyone have any idea what to do with it?
Thanks,
Michal Dudka

[Michal Dudka]

To rule out DMA related problems i've made another observations:

I am feeding PSSI manually in while loop by following code:

while (1){
  if(PSSI->SR & PSSI_SR_RTT4B){
	  PSSI->DR = arr[idxx];
	  idxx++;
	  if(idxx >= BLOCK_SIZE){
		  LL_GPIO_SetOutputPin(GPIOB, LL_GPIO_PIN_8);
		  delay(1000);
		  idxx = 0;
		  cnt++;
		  if(cnt >= 16){
			cnt = 0;
		  }
		  LL_GPIO_ResetOutputPin(GPIOB, LL_GPIO_PIN_8);
	  }
    }	
  }
}
  

without "delay()" everythings work fine, and DE is never deasserted (PSSI buffer have some data all the time). When "delay()" added, to make some times with DE deasserted, then appears interesting signal traces. Look at following scope traces:
Stop transmission due RDY and then DE deassert
suspicious manipulating with data during DE deassertTransmitting "correct" data (or two byte lost)

There you can see that reciever stops transmiting by RDY deassert when read "1" data. PSSI place new data ("0") on bus and coincidentally deasserts DE few ticks later. Then reciever asserts RDY back and PSSI for unknown reasons manipulates with DATA. DE is deasserted, therefore the receiver did not read the data (0) and there is no reason to change data (to 1). At the end, you can see that when DE is asserted, then data is moved again to 0. In recieved data i see missing two bytes.

Reference manual (RM0477 Rev 8) claims in 32.3.5 
Reference Manual

If I interpret it correctly, it should mean that the data does not change when DE is inactive. But i have observed change in DATA during DE inactive (middle one scope screenshot).