PM0056 issues: NVIC_IPR20 offset incorrect
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‎2024-09-17 09:21 AM - last edited on ‎2024-09-17 10:13 AM by Andrew Neil
I calculated the last address is 0x350
Is it a problem with the manual?
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‎2024-09-17 09:29 AM
https://electronics.stackexchange.com/questions/450897/nvic-memory-map-arm-cortex-m3-stm32f103
Yes, and the overall depth for IP[x] is not defined, it depends on specific implementation and the interrupt count in each.
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‎2024-09-17 08:44 PM
Don't sink my post.
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‎2024-09-17 10:09 PM - edited ‎2024-09-18 06:58 AM
Huh?
It's definitely incorrect, but been in there for years. Most would use the structure, or the ARM TRM's
Several people have been alerted to this issue.
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‎2024-09-17 11:09 PM
Oh! It is normal to make mistakes in the manual, but it is disappointing that a problem that has existed for many years has not been corrected. Thank you for your answer.
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‎2024-09-17 11:52 PM - edited ‎2024-09-18 12:56 AM
Hello @ljh and welcome to the ST Community.
Thank you so much for reporting this. I've escalated to the concerned team for correction on the coming releases (under internal ticket number 191372). Thank you @Tesla DeLorean for the mention.
Best Regards.
STTwo-32
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‎2024-09-18 07:04 AM
No, well from my view point, whilst it's unfortunate, there are enough more authoritative sources of information that could be used to establish facts. The problems with these types of documents is that they try and cover too many divergent products. There are issues with cut-n-paste from prior documents, evolution and transposition of digits and bases.
Other affirming sources if the math looks janky, Include files, .SVD files, ARM's docs.
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