On the stm32l486 the port GPIOG, pins 3-15 do not appear to be working when configured as outputs

[WMcKi.1924]

I have a new product using the stm32l486, and the GPIOG pins mentioned in the title do not appear to work as outputs, even though they are configured identically to the GPIO pins I am using for ports A-F. I cannot find anything in either the datasheet or the user manual about any pecularities to port G. But when pins in the GPIOG.ODR are set to '1' they definitely do not go high, and they are still read back as '0' on GPIOG.IDR. I also do not see anything in the errata for the stm32l486. I am correct in thinking that port G works like the other ports on this part?

[waclawek.jan]

These pins are powered by VDDIO2. Do you have VDDIO2 properly connected?

Not very conspicuously, but it's said both in DS (these pins are marked with suffix _s (or _fs) in the pin definitions table, with the explanation at beginning of the table) and RM (in PWR/Power supplies chapter:

V DDIO2 is the external power supply for 14 I/Os (Port G[15:2]). The V DDIO2 voltage level

is independent from the V DD voltage and should preferably be connected to V DD when

PG[15:2] are not used.

JW

[WMcKi.1924]

Our board has VDDIO2 connected to VDD. So G[15:2] should be working, correct?

[waclawek.jan · Accepted solution]

Oh, and I forgot - read 5.1.2 Independent I/O supply rail in RM:

After reset, the I/Os supplied by V DDIO2 are logically and electrically isolated and therefore

are not available. The isolation must be removed before using any I/O from PG[15:2], by

setting the IOSV bit in the PWR_CR2 register, once the V DDIO2 supply is present.

JW

[WMcKi.1924]

Yep, that's my problem. Needed to hit RCC_APB1ENR1_PWREN in RCC->APB1ENR1 and IOSV in PWR->CR2. Thank you very very much. I'm seeing mentions of those pins in the data sheet now. Thank you also for pointing that out and for the prompt and accurate response.

--b

[WMcKi.1924]

I don't see a close button on this page. How do I close this request?

[Tesla DeLorean]

On L4+ we have this in SystemClock_Config()

   __HAL_RCC_PWR_CLK_ENABLE();
  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); /* Enable voltage range 1 boost mode for frequency above 80 Mhz (L4+) */
  HAL_PWREx_EnableVddIO2(); /* IOSV bit MUST be set to access GPIO port G[2:15] */
  __HAL_RCC_PWR_CLK_DISABLE();