In RM0433 revision 5 section 3.3.8, the following text appears: “To correctly read data from Flash memory, the number of wait states (LATENCY) must be correctly programmed in the Flash access control register (FLASH_ACR) according to the embedded Flash memory AXI interface clock frequency (sys_ck) and the internal voltage range of the device (V core ).�? However, according to figure 45 in section 7.5.6, the AXI interface clock is rcc_aclk, not sys_clk; the former can be up to 200 MHz while the latter can be up to 400 MHz; sys_clk is divided by D1CPRE and then HPRE to get rcc_aclk. So which frequency needs to be used to calculate Flash wait states? Table 12 in the reference manual only has entries up to 225 MHz, suggesting that it’s actually rcc_aclk and not sys_clk, but it would good to know for sure.
It’s also unclear what the maximum frequency of rcc_aclk actually is; figure 45 in the reference manual has a “200 MHz Max�? note on a line leading to rcc_aclk, but page 108 of DocID030538 states that current consumption was measured with FACLK up to 400 MHz.
