NVIC

[MTS]

Hi guys. please tell me why you don't do enough NVIC? for example, when several timers are running, and it is necessary to parallelize tasks so that interrupts from each timer happen independently, but now until one interrupt comes out, the other will not be processed. with multi-core CPUs and parallel computations, it would be good if there were 2< NVIC

[MTS]

there are no problems with processor cores, then there may be one of them M4 and the other M7. the point is that if you do not redesign the architecture of the microcontroller, then this is the way to the end. it is necessary to make microcontrollers more flexible in programming interrupt priorities cannot solve the problem that almost all microcontrollers in this company have. even a single core could handle multiple interrupts at once and not in turn. I have already written about this above. they need to understand that the architecture of microcontrollers needs to be developed so that at any moment something new can be added without any major changes to the entire architecture as a whole. now, in order to add something new, they need to revise everything and link it all with each other. such an approach as interrupts in turn without the possibility of simultaneous processing of several interrupts will become a huge problem in the future and this may be the reason why such an architecture will not be able to develop any more and you will have to give up everything and develop a new one. therefore, it is necessary to think now taking into account the future. you need to understand that in the future you will have to add something to the architecture and think about how it will all interact with the existing ones. I say again that one NVIC and the inability to handle multiple interrupts at once will become a dead end in the future.

[Danish1]

Perhaps what you don’t realise is that an NVIC is not capable of executing code. All it can ever do is tell the Arm processor to which it’s attached to stop what it is doing and instead execute higher-priority interrupt code.

An NVIC peripheral is only a few hundred transistors big.

A processor core, with the ability to execute code, is tens if not hundreds of thousands of transistors big.

More transistors means more chip area so higher price, and also higher current leakage i.e. consumption even when not doing anything.

Although it would be great to be able to execute more threads simultaneously (whether they are “interrupts” or just different tasks for main program functionality) adding more NVICs without more processor-cores cannot do this.

The future might have more designs with the capability to execute more simultaneous threads, so more processor cores. And there’s nothing stopping ST from making such offerings. Arm has high-performance designs with multiple cores and the associated complications. But for many systems using microcontrollers they do not represent a good compromise.

[LCE]

>  the bottom line is that timers should be able to work independently

You think they don't? Then have another look at the hardware.

It seems that you are new to "microcontrollers". These are made for embedded systems, low power and space consumption. They are simply not "multi-core desktop CPUs", neither are they FPGAs.

If you need faster parallel processing, build your own controller inside an FPGA.

Somehow funny to question the ARM µC structure in general as a beginner!
But I understand somehow, I started working with FPGAs before using microcontrollers, and I was shocked at first that they could just not do anything in parallel! 😉

But you get used to it, and with smart ISRs and ample use of the DMA controllers you'll get close to "parallel".