Nucleo STM32H723ZG ADC 75 MHz or 5MSPS or maximal sample rate

[OMarq.1]

Hello everyone,

I hope you’re all doing well! I’m currently struggling to get one of the directly connected ADCs on the STM32H723ZG working at 75 MHz, which is the maximum sample rate according to the datasheet.

I’ve selected ADC3_INP1 since it’s supposed to be one of the four fastest channels available. I’ve attached a picture of my configuration, but I’m having trouble with the clock setup. The system can't find any configuration that achieves the desired 75 MHz for the ADC. The best I’ve managed is to manually adjust PLL2 to get bit higher than 76 MHz, but that doesn’t feel quite right. I need high accuracy for several measurements, and I know the MCU cannott exceed 75 MHz for the direct ADCs at 12 bits.

As you can see in the picture of the clock configuration, the system is connected to a 50 MHz external crystal, and the system clock is set to 300 MHz. This setup is intended to achieve 75 MHz for the peripheral clocks attached to APB1, which includes DAC1 and DAC2, that I plan to use later at that frequency.

(I use ADC3, which is connected to PC2_C and/or PC3_C. However, I’m having difficulty finding an available pin on the board to test PA1_C in the UM2407 user manual is not to find. If anyone knows where this pin might be located, I would greatly appreciate your guidance)

Thank you all for your help!

[MasterT]

Datasheet says max 50 MHz.

https://www.st.com/en/microcontrollers-microprocessors/stm32h723zg.html#documentation

p. 185

[OMarq.1]

Dear MasterT,

Thank you for your extremely kind reply. Perhaps I am misunderstanding the information from the MCU datasheet regarding the attached segments...

   

Additionally, STM32CubeIDE keeps indicating that the maximum ADC clock source frequency is 60 MHz, which is inconsistent with your thoughtful reply and what I found regarding the directly connected 12-bit ADC for this chip.

I would be grateful if someone could help me understand this issue with the clock system and where to find a usable pin for PA1_C on this Nucleo.

Thank you!

[Ozone]

I think you should consult reference manual and datasheet of the H723 variant. I never worked with this part.

But the achievable clock frequency of a peripheral also depends on the (internal) bus it is connected to. And not every peripheral bus supports all possible clock divider ratios. I suppose the H7 does not differ from F4, F4 and F7 parts in this regard.

You might even need to reduce the core clock frequency to achieve this 75MHz ADC clock directly.

[LCE]

ADC clock frequency is not the same as sampling rate!

Check the datasheet, "Electrical Characteristics / ADC".

Also check the reference manual for register settings.

You can't always trust CubeMX...

[MasterT]

You didn't mention 12-bits adc. There are two kinds, 16-bits & 12-bits, and 16-bits could run 5 MSPS in 14-bits mode as well. 

You are right, that CubeMX limits frequency to 60 MHz, definitely bug. There should be a link somewhere to report such software bugs to developers of CubeMX directly. For myself, I 'd ignore warning and set frequency prescribed by DS, not to wait new CubeMX patch

Regarding pin PC1 , you can always locate any pin using schematic of nucleo board (under CAD tab), PC1 seems busy by Ethernet, and if it's not in use you  can make pin free by desoldering bridge SB64