NUCLEO-H723ZG ethernet issue with Keil uVision5 / MDK-ARM

[Frank H]

Hi guys,

I started a project on keil µVision5.34 and a NUCLEO-H723ZG board. I would like to implement TCP-IP connection with a computer.

After receiving an ARP request from the computer, the microcontroller enters in hardfault_handler. So it doesn't send its MAC address, and the TCP handshake can't be executed.

Here I give you the description of my project :

1.     In µVision RTE selection :

CMSIS -> CORE Enabled

CMSIS -> RTOS2 (API) -> Keil RTX5 Enabled, Source

CMSIS Driver -> Ethernet MAC (API) -> Ethernet MAC enabled

CMSIS Driver -> Ethernet PHY (API) -> LAN8742A enabled

Compiler -> Event Recorder enabled

Compiler -> I/O -> STDOUT enabled, EVR

Device -> Startup enabled

Device -> STM32Cube Framework (API) -> STM32CubeMX enabled

Device -> STM32Cube HAL -> common enabled

Device -> STM32Cube HAL -> Cortex enabled

Device -> STM32Cube HAL -> DMA enabled

Device -> STM32Cube HAL -> ETH enabled

Device -> STM32Cube HAL -> GPIO enabled

Device -> STM32Cube HAL -> PWR enabled

Device -> STM32Cube HAL -> RCC enabled

Network MDK-Pro

Network -> Core enabled, IPv4 Debug STDIO

Network -> Interface -> ETH to 1

Network -> Socket -> TCP enabled

2.     In STM32CubeMX :

Clock config -> SYSCLK 400 MHz / Peripheral clocks 200 and 100MHz

Connectivity -> ETH -> Mode RMII / Parameters by default ( @MAC:00:80:E1:00:00:00 / Tx Desciptor length : 4 / First Tx Descriptor @ 0x30040060 / Rx descriptor Length : 4 / first RX descriptor @ 0x30040000 / Rx Buffer @ : 0x30040200 / Rx Buffers Length : 1524)

I redirected ETH_TXD0 on PG13 and ETH_TX_EN on PG11 which are the pin used on the nucleo board

I set all GPIO pin to High

System Core -> NVIC -> NVIC -> Ethernet global interrupt enabled

System Core -> NVIC -> Code generation -> generate IRQ handler disabled for System service call via SWI instruction, Pendable request for system service and Time base : System tick timer

This is required to use RTX5 which already use these IRQ_handler

PC13 declared as EXTI, and PB0, PE1 and PB14 as DO to drive 3 Leds that blink if program is running

System Core -> Cortex_M7 configured as described in "EMAC_STM32H7xx.c" (CMSIS Driver)

     CPU_ICache enable

     CPU_DCache enabled

     MPU Control Mode : Background Region Privileged accesses only + MPU Disabled

     Cortex MPU Region 0 -> MPU region enable

Cortex MPU Region 0 -> Base @ : 0x30040000

Cortex MPU Region 0 -> Region size : 32KB

Cortex MPU Region 0 -> Subregion disabled

Cortex MPU Region 0 -> TEX filed level : 1

Cortex MPU Region 0 -> Access permission : all access permitted

Cortex MPU Region 0 -> instruction disabled

Cortex MPU Region 0 -> shareability disabled

Cortex MPU Region 0 -> cacheable disabled

Cortex MPU Region 0 -> bufferable disabled

Cortex MPU Region 1 -> MPU region enable

Cortex MPU Region 1 -> Base @ : 0x30040000

Cortex MPU Region 1 -> Region size : 256KB

Cortex MPU Region 1 -> Subregion disabled

Cortex MPU Region 1 -> TEX filed level : 0

Cortex MPU Region 1 -> Access permission : all access permitted

Cortex MPU Region 1 -> instruction disabled

Cortex MPU Region 1 -> shareability enabled

Cortex MPU Region 1 -> cacheable disabled

Cortex MPU Region 1 -> bufferable enabled

                       Generate the project

3.     Net_Config_ETH_0.h : IPV6 disabled, NetBIOS Name Service disabled, Dynamic Host Conf disabled. Rest as default

Net_Debug.c : IPv4 Core Debug : Full Debug and Socket debug : full debug

4.     Options for target -> Linker -> Scatter File : I put the scatter file of the STM32CubeMX example for the NUCLEO-H723ZG board : LwIP_TCP_Echo_Server

As suggested in : https://community.st.com/s/question/0D50X00009XkYKNSA3/problem-with-network-component-on-stm32h7-cubemx-and-keil

5.     On main.c generated by CubeMX i added (as described in CMSIS doc) RTX initialization and app_main.c thread starting

6.     I created a file app_main.c and i added the content of the User Code Template : Network -> Socket : TCP -> TCP Socket Server

I enabled the SRAM2 clock in this file

Compilation is OK

After startup the chip boots and start netInitialize routine. After that i launched an exe on my comptuter which start communication with the board. microtronller enter in hardfault after receiving the ARP request without sending its response.

On wireshark the ARP request appears without response :

Source : goodWayI_58:22:35 Destination: Broadcast, Protocol : ARP, Length : 42, Info : Who has 192.168.0.100? Tell 192.168.0.10

I saw that stm32h723 has seen this request on debug console, but enters in hardfault IRQ when it tries to send his response.

Do you have an idea what i may be missing ?

you'll find attached the code added in main.c

Thanks,

Frank

Here the debug console :

000.0 SYS:Init Network 7.14.0

000.0 ETH:Init_interface 0

000.0 ETH: MAC (1E-30-6C-A2-45-5E)

000.0 IP4:Init Core, Default ETH0

000.0 ARP:Init_cache ETH0, 10 entries

000.0 ICMP:Init Client

000.0 TCP:Init 6 Sockets

000.0 TCP: MaxSegSize=1440

000.0 SYS:Init complete

000.0 TCP:Get Socket 1

000.0 TCP:Listen Socket 1, Port 52000

001.9 ETH:Link 0 up

001.9 ETH: 100M, Full duplex

002.0 ETH:*** Process_frame 0 ***

002.0 ETH: DstMAC FF-FF-FF-FF-FF-FF

002.0 ETH: SrcMAC 00-50-B6-58-22-35

002.0 ETH: Proto ARP, 60 bytes

002.0 ARP:*** Process_frame ETH0 ***

002.0 ARP: Opcode ARP-REQUEST

002.0 ARP: SendIp 0.0.0.0

002.0 ARP: TargIp 192.168.0.10

002.0 ARP: SendMac 00-50-B6-58-22-35

002.0 ARP: TargMac 00-00-00-00-00-00

002.0 ARP: Discarded, SendAddr invalid

002.8 ARP:*** Process_frame ETH0 ***

002.8 ARP: Opcode ARP-REQUEST

002.8 ARP: SendI68.0.10

002.8 ARP: TargIp 192.168.0.100

002.8 ARP: SendMac 00-50-B6-58-22-35

002.8 ARP: TargMac 00-00-00-00-00-00

002.8 ARP:Cache_add ETH0

002.8 ARP: IP4 192.168.0.10

002.8 ARP: MAC 00-50-B6-58-22-35

002.8 ARP: Entry 1 added

002.8 ARP:Send_reply ETH0

002.8 ARP: Opcode ARP-REPLY

002.8 ARP: SendIp 192.168.0.100

002.8 ARP: TargIp 192.168.0.10

002.8 ARP: SendMac 1E-30-6C-A2-45-5E

002.8 ARP: TargMac 00-50-B6-58-22-35

002.8 ETH:Output 0, 42 bytes