2023-11-08
01:19 PM
- last edited on
2023-11-09
06:52 AM
by
Lina_DABASINSKA
Cross-references the wrong register, should be RCC_BDCR
RM0394 Reset and clock control (RCC) Pg 247
6.2.6 LSE clock
...
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR). The external clock signal (square, sinus or triangle) with ~50 % duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as GPIO. See Figure 14.
2023-11-08
10:23 PM
- last edited on
2023-11-09
05:36 AM
by
Lina_DABASINSKA
Hello @Tesla DeLorean,
Thank you for reporting this. I will check it internally and get back to you as soon as possible.
Best Regards.
STTwo-32
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2023-11-08 11:19 PM
I've escalated this to the appropriate team for correction of RM0394 with internal ticket ID165919.
(PS: ID165919 is an internal tracking number and is not accessible or usable by customers)
thank you for your contribution.
Best Regards.
STTwo-32.
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.