As all other bits in that register, this also enables clock to one of the modules - here, PWR, as documented in chapter 7. That's why the bit is called PWREN, as in PWR ENable.
After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF).
Before using a peripheral user has to enable its clock in the RCC_AHBENR,
RCC_APB2ENR or RCC_APB1ENR register.
JW
