STM32N6 FMC LCD Interface: Spurious WR pulses; No MPU configuration generated

[mraehle]

Hi community

I found a missconfiguration in CubeMX while using a MCU TFT with FMC.

Description:

Device: STM32N6 (STM32N645B0HxQ) / Cortex-M55

CubeMX Version: v6.17.0

Peripheral: FMC, LCD Interface, 16-bit data width, A16 as RS/DC (Register Select)

Symptom: A single WriteCommand() call (one STRH instruction to 0x60000000) produces 3 WR pulses on the oscilloscope instead of 1. The LCD display remains gray despite a correct initialization sequence. All FMC timing parameters and Write FIFO settings were verified and are not the cause.

Root Cause: The Cortex-M55 (ARMv8-M) treats 0x60000000 as Normal Memory by default. This allows the CPU to merge and reorder 16-bit write accesses into 64-bit bursts, resulting in multiple spurious WR pulses on the FMC bus. The LCD controller receives garbage data and cannot render anything.

Solution: Manually configuring an MPU region for 0x60000000–0x63FFFFFF as Device nGnRnE memory resolves the issue immediately. After applying the MPU config, exactly 1 WR pulse is observed per write operation and the display works correctly.

static void MPU_Config_LCD(void)
{
    ARM_MPU_Disable();

    // Attribute 0: Device-nGnRnE (Strongly Ordered)
    MPU->MAIR0 = (MPU->MAIR0 & 0xFFFFFF00UL) | 0x00UL;

    // Region 0: FMC LCD area
    MPU->RNR  = 0UL;
    MPU->RBAR = (0x60000000UL & MPU_RBAR_BASE_Msk)
              | (0UL << MPU_RBAR_SH_Pos)
              | (1UL << MPU_RBAR_AP_Pos)
              | (1UL << MPU_RBAR_XN_Pos);
    MPU->RLAR = (0x63FFFFFFUL & MPU_RLAR_LIMIT_Msk)
              | (0UL << MPU_RLAR_AttrIndx_Pos)
              | (1UL << MPU_RLAR_EN_Pos);

    MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk;
    __DSB();
    __ISB();
}

CubeMX Gap: CubeMX does not generate MPU configuration code when the FMC is configured as LCD Interface. The warning tooltip on the FMC peripheral mentions timing and pin conflicts but gives no indication that an MPU region must be manually configured for correct operation. This is especially critical for STM32N6 / Cortex-M55, where the default memory map changed compared to Cortex-M4/M7 based STM32 devices.

Suggested Improvement: When FMC is configured as LCD Interface on Cortex-M55 based devices, CubeMX should either:

• Automatically generate the required MPU region as Device memory, or
• Display an explicit warning: "The FMC address range must be configured as Device memory in the MPU to prevent spurious write accesses."

Related Community Thread: "STM32H743II FMC + 8080 LCD spurious writes" https://community.st.com/t5/stm32-mcus-touchgfx-and-gui/stm32h743ii-fmc-8080-lcd-spurious-writes/td-p/354191 (Same root cause, reported for STM32H7 – now also confirmed on STM32N6)

thanks Markus