Minimum pulse width for STM32F2 timer in input capture mode.

[RGadd.2]

I have a low frequency (~1 kHz), low duty cycle signal that I'd like to capture rising edges of. What's the minimum width of those pulses to capture them using a timer in input capture mode?

I see there's a programmable digital filter there, in terms of fDTS and ***_INT, and that the latter is the respective APB bus clock (but divided by no more than 2 from SYSCLK). But what dictates fDTS?

[Tesla DeLorean · Accepted solution]

TIMCLK = APBCLK *2 or *1 depending on the APB divider

fDTS = TIMCLK / ClockDiv field for the TIM, ie CKD bits in TIMx_CR1

[RGadd.2]

Perfect, that's what I was missing. Thanks for the help.