LSE Gain margin

okeskin_mak · ‎2022-10-13

Hi,

I am using a crystal from AN2867 (ECX-.327-CDX-1293). I'm having trouble starting LSE on stm32g474 mcu.

When I calculate gain Margin, I reach 1.24. The expression in the application note also tells us to be careful that the oscillator transconductance value is greater than 5.(AN2867 Rev 16- Page:13).

High drive capability consumes high energy and does not provide sufficient gain margin.

The crystal suggested in the app note wants a load capacitance of 12.5pf. I'm using 15pF considering the stray capacitance(AN2867 Rev 16- Page:12).

What am i missing?

waclawek.jan · ‎2022-10-13

Don't be focused on gain margin and calculations, there are many factors which can make LSE unoperable, perhaps the most important is layout.

So post pictures, describe what have you done and what are your findings.

Also, try a "known good" board such as Nucleo.

JW

okeskin_mak · ‎2022-10-14

Hi JW,

I checked the nucleo. It uses the NX3215SA crystal. I also looked at the layouts. transported by jumpers and vias. Even the parasitic effect of vias is not on my card. The point I got stuck on is using 5.1pf capacity for a crystal with 6pf load capacity. this gives a value of 3.45 pf for the stray capacity.

I am sharing the layout. I am trying to understand . What should I do with CL1 and CL2? Is the cs actually determined by experiment or does it matter at all?

BR.

Peter BENSCH · ‎2022-10-14

There was a similar discussion a few months ago. In your case, I suspect that GND under the crystal is not optimally designed. Take a close look at sections 7.1 and 7.2 from AN2867, especially figures 13..16, and you will know what I mean.

Regards

/Peter

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waclawek.jan · ‎2022-10-14

I think what Peter talks about in this particular case mostly translates to: don't connect the ground/return from capacitors to the ground plane at the crystal, rather, bring it with a separate track the shortest possible way to the GND pin closest to crystal pins on the mcu..

What you can do, experimentally, is to carefully drill out (or just an annulus around it to disconnect) the via connecting to ground plane and connect the ground with a shortest possible wire to said closest GND pin.

Also, make sure you don't have any solder residua on and around the oscillator's tracks/pins.

Also, we still don't know what are your findings, exactly. You may want to reduce unknowns by writing a minimal code which does nothing but enable LSE and output it to a MCO pin or similar.

Note, that probing LSE with oscilloscope significantly loads the oscillator and dramatically influences its working.

JW

okeskin_mak · ‎2022-10-14

Hi JW,

I understand what you're saying. Only one issue that I did not specify, the startup problem does not exist on all pcbs. Some products start directly without problems. Initially I tried with LSE low drive. Then none of them worked. When I tried it with the high drive, I only discovered a few startup failures. This doesn't make sense. I agree that the layout can be problematic but somehow some of them work. It's starting to seem like the only factor is capacity. Which brings me to the gain margin calculation.

okeskin_mak · ‎2022-10-14

Hi Peter,

You're right about the GND plane, I'll have to change it. However, we produced dozens of cards for prototype production. I'm having some startup issues.

Also, my pcb doesn't even have a via. It uses via and jumper in Nucleo kit but still ok???

This unstable operation is incredibly risky for a serial product. Isn't gain margin guaranteed that I won't experience this even with the right design?