cancel
Showing results for 
Search instead for 
Did you mean: 

Clarification on LSE Crystal Drive Level and Gmcritmax for NUCLEO-WB55 LSE Oscillator

NirAlon
Associate III

Hello everyone,

I’m working with the NUCLEO-WB55 (MB1355D-01) board, and looking at its LSE crystal, the NX2012SA 32.768 kHz with ESR ~120 kΩ and load capacitance 6 pF (Datasheet attached).

Calculating the crystal’s minimum transconductance (Gₘ) using:

Gm=4×ESR×(2πf)^2×(C0+CL)^2 ≈ 1.1μA/V

From the STM32WB55 datasheet, the maximum critical crystal gm (Gmcritmax) values depending on the LSEDRV drive setting are:

  • 00 (Low): 0.50 µA/V

  • 01 (Medium low): 0.75 µA/V

  • 10 (Medium high): 1.70 µA/V

  • 11 (High): 2.70 µA/V

My software engineer mentioned ST uses the lowest drive setting (00) for the LSE oscillator by default, but based on the crystal’s Gₘ, this seems insufficient for reliable oscillation on the NUCLEO board.

Given the crystal Gₘ is around 1.1 µA/V (above the lowest and medium low drive thresholds), how does the LSE oscillator function properly on the NUCLEO-WB55/EVM board? Even at the highest drive level, the margin seems small.

  • Is ST actually using a higher drive level on the EVM/Nucleo boards?

  • How is the margin managed to ensure stable startup and oscillation?

Thanks!

Nir

6 REPLIES 6
NirAlon
Associate III

Anyone?

Nir

AScha.3
Super User

Hi,

i always use high drive on the LSE , to have it always 100% running.

(I dont worry about the 3uW "wasted" energy ... but i worry about a possibly not starting LSE . :)

 

+

The default, lowest drive level, is a problem with many crystals, so just dont use it, if you didnt test with the matching crystals , and at different temperatures etc. ;

Why STM doing this...ask them, if you like...

just set hi drive and test it. Should work fine, with all LSE crystals. (in my tests it did.)

If you feel a post has answered your question, please click "Accept as Solution".

Hi,

Thanks for your reply, Did you check whether setting the drive strength to max (LSEDRV = 11) causes the crystal’s drive level to exceed its maximum specified value? (0.5uW in the above case)

Thanks again,

Nir

STTwo-32
ST Employee

Hello @NirAlon 

I suggest you follow the recommendation of the DS13252. it should be helpful for you:

STTwo32_0-1754297564667.png

Best Regards.

STTwo-32

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

>Did you check whether setting the drive strength to max

To be true : never.

Measuring drive level ...is not easy:

https://www.allaboutcircuits.com/technical-articles/measuring-drive-level-of-a-quartz-crystal/

 

So i never worried about the drive level, but having a not starting or stable running oscillator,

IS a big problem: it stops the whole machine . 

So ( at work ) i defined: we use hi drive always, to have no machines not working, because the LSE stopped working.

And now thousands of boards running around the world (many since years 24/7 ) and no problem with the clocks.

+

About the drive level /power at your WB55 ...see ds, power... , without any measurement :

AScha3_0-1754299189256.png

So it consumes typ. 500nA at 3 V , = > 1.5 uW ;  what can it drive now "dangerous power" to the crystal?

assuming a 50% efficiency , all is 0.7 uW , thats possible at its max. "power" ....come on. Dangerous ? Joking, eh ? :)

 

 

If you feel a post has answered your question, please click "Accept as Solution".

Measuring drive level is not so difficult when using an active probe:

(AN2867 Rev 23 page 16)

NirAlon_0-1754302852202.png

 

Anyway, I’ll measure the DL to ensure everything is within spec when set to max level.

Thanks

Nir