2025-07-29 1:57 AM
Hello everyone,
I’m working with the NUCLEO-WB55 (MB1355D-01) board, and looking at its LSE crystal, the NX2012SA 32.768 kHz with ESR ~120 kΩ and load capacitance 6 pF (Datasheet attached).
Calculating the crystal’s minimum transconductance (Gₘ) using:
Gm=4×ESR×(2πf)^2×(C0+CL)^2 ≈ 1.1μA/V
From the STM32WB55 datasheet, the maximum critical crystal gm (Gmcritmax) values depending on the LSEDRV drive setting are:
00 (Low): 0.50 µA/V
01 (Medium low): 0.75 µA/V
10 (Medium high): 1.70 µA/V
11 (High): 2.70 µA/V
My software engineer mentioned ST uses the lowest drive setting (00) for the LSE oscillator by default, but based on the crystal’s Gₘ, this seems insufficient for reliable oscillation on the NUCLEO board.
Given the crystal Gₘ is around 1.1 µA/V (above the lowest and medium low drive thresholds), how does the LSE oscillator function properly on the NUCLEO-WB55/EVM board? Even at the highest drive level, the margin seems small.
Is ST actually using a higher drive level on the EVM/Nucleo boards?
How is the margin managed to ensure stable startup and oscillation?
Thanks!
Nir