LPDMA Update Link Error

[AlwaysFlyingMonkey]

static uint16_t aDST_Buffer_1[BUFFER_SIZE] = {0};
static uint16_t aDST_Buffer_2[BUFFER_SIZE] = {0};
LL_DMA_LinkNodeTypeDef pNode1, pNode2;

/**
 * @brief LPDMA1 transfer configuration
 * @PAram None
 * @retval None
 */
void BspLPDMA1Init(void)
{
/* DMA node configuration declaration */
LL_DMA_InitNodeTypeDef DMA_InitNodeStruct;
LL_DMA_InitLinkedListTypeDef DMA_InitLinkedListStruct;

/* Set node configuration ################################################*/
/* Set node type */
DMA_InitNodeStruct.NodeType = LL_DMA_LPDMA_LINEAR_NODE;

/* Set node configuration */
DMA_InitNodeStruct.BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
DMA_InitNodeStruct.Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY;
DMA_InitNodeStruct.DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT1;
DMA_InitNodeStruct.DestBurstLength = 1U;
DMA_InitNodeStruct.DestIncMode = LL_DMA_DEST_INCREMENT;
DMA_InitNodeStruct.DestDataWidth = LL_DMA_DEST_DATAWIDTH_HALFWORD;
DMA_InitNodeStruct.SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0;
DMA_InitNodeStruct.SrcBurstLength = 1U;
DMA_InitNodeStruct.SrcIncMode = LL_DMA_SRC_INCREMENT;
DMA_InitNodeStruct.SrcDataWidth = LL_DMA_SRC_DATAWIDTH_HALFWORD;
DMA_InitNodeStruct.TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER;

/* Set node data handling parameters */
DMA_InitNodeStruct.DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
DMA_InitNodeStruct.DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE;
DMA_InitNodeStruct.DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE;
DMA_InitNodeStruct.SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE;

/* Set node trigger parameters */
DMA_InitNodeStruct.TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED;

/* Set repeated block parameters */
DMA_InitNodeStruct.BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT;
DMA_InitNodeStruct.BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT;
DMA_InitNodeStruct.DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT;
DMA_InitNodeStruct.SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT;
DMA_InitNodeStruct.BlkRptCount = 0U;
DMA_InitNodeStruct.DestAddrOffset = 0U;
DMA_InitNodeStruct.SrcAddrOffset = 0U;
DMA_InitNodeStruct.BlkRptDestAddrOffset = 0U;
DMA_InitNodeStruct.BlkRptSrcAddrOffset = 0U;

/* Set registers to be updated */
DMA_InitNodeStruct.UpdateRegisters = DEFAULT_REGISTER_UPDATE;

/* Set transfer parameters */
DMA_InitNodeStruct.BlkDataLength = (BUFFER_SIZE * 2U);

/* Initializes DMA linked list node */
DMA_InitNodeStruct.SrcAddress = (uint32_t)aDST_Buffer_1;
DMA_InitNodeStruct.DestAddress = (uint32_t)aDST_Buffer_2;
LL_DMA_CreateLinkNode(&DMA_InitNodeStruct, &pNode1);

DMA_InitNodeStruct.SrcAddress = (uint32_t)aDST_Buffer_2;
DMA_InitNodeStruct.DestAddress = (uint32_t)aDST_Buffer_1;
LL_DMA_CreateLinkNode(&DMA_InitNodeStruct, &pNode2);

/* Build linked-list Queue #################################################*/
/* Connect Nodes */
LL_DMA_ConnectLinkNode(&pNode1, LL_DMA_CLLR_OFFSET5, &pNode2, LL_DMA_CLLR_OFFSET5);
LL_DMA_DisconnectNextLinkNode(&pNode2, LL_DMA_CLLR_OFFSET5);

/* Initialize DMA channel ##################################################*/
/* Enable DMA clock */
LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_LPDMA1);

/* Set DMA channel parameter to be configured */
DMA_InitLinkedListStruct.Priority = LL_DMA_HIGH_PRIORITY;
DMA_InitLinkedListStruct.TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER;
DMA_InitLinkedListStruct.LinkStepMode = LL_DMA_LSM_FULL_EXECUTION;
DMA_InitLinkedListStruct.LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT1;

/* Initialize the DMA linked list */
LL_DMA_List_Init(LPDMA1, LL_DMA_CHANNEL_0, &DMA_InitLinkedListStruct);

/* Link created queue to DMA channel #######################################*/
LL_DMA_SetLinkedListBaseAddr(LPDMA1, LL_DMA_CHANNEL_0, (uint32_t)&pNode1);
LL_DMA_ConfigLinkUpdate(LPDMA1, LL_DMA_CHANNEL_0, DEFAULT_REGISTER_UPDATE, (uint32_t)&pNode1);

/* Enable DMA interrupts */
LL_DMA_EnableIT_USE(LPDMA1, LL_DMA_CHANNEL_0);
LL_DMA_EnableIT_ULE(LPDMA1, LL_DMA_CHANNEL_0);
LL_DMA_EnableIT_DTE(LPDMA1, LL_DMA_CHANNEL_0);
LL_DMA_EnableIT_TC(LPDMA1, LL_DMA_CHANNEL_0);

/* DMA channel 0 interrupt init */
NVIC_SetPriority(LPDMA1_Channel0_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),2, 3));
NVIC_EnableIRQ(LPDMA1_Channel0_IRQn);

/* Enable DMA channel */
LL_DMA_EnableChannel(LPDMA1, LL_DMA_CHANNEL_0);
}

The software enters LPDMA_IRQHandler() after the execution of BspLPDMA1Init().

A Update Link Error is found in LPDMA_IRQHandler().

Please help me see what causes it.

[Sarra.S · Accepted solution]

Hello @AlwaysFlyingMonkey, welcome to ST Community

The LPDMA1 (see RM figure 2.SmartRun domain architecture) is master on the SRD 32-bit bus matrix. Consequently, LPDAM can only use the SRAM4 space that is allowed in the SRD domain. There is no way to access SRAM1,2,3 by LPDMA according to this architecture.

So, the 'Update Link Error' in LPDMA_IRQHandler() could be due to the location of your DMA linked list Nodes & QLists, as well as the buffers used. It's suggested to place these in the SRAM4 region by modifying your stm32u575xx_flash.icf file

Please try that and let us know!

Thank you! 

[AlwaysFlyingMonkey]

__attribute__((section(".sram4"))) static uint16_t aDST_Buffer_1[BUFFER_SIZE] = {0};

__attribute__((section(".sram4"))) static uint16_t aDST_Buffer_2[BUFFER_SIZE] = {0};

__attribute__((section(".sram4"))) LL_DMA_LinkNodeTypeDef pNode1, pNode2;

I solve this problem by adding buffer and node in SRAM4.

Thank you.