Hi everyone,
I’m encountering problems with SPI communication with the board NUCLEO-H753ZI and the EVAL-AD5764 from Analog Devices, as this is my first time working with it, and I’m unsure if I’ve configured it correctly.
I’ve consulted a forum for Analog Devices, and they pointed out that I’m incorrectly generating the CLK signal.
Specifically, I’m trying to transmit a 24-bit signal, aiming for 24 rising edges and 24 falling edges of the CLK signal while the CS line is low. However, when I use HAL_SPI_Transmit, I observe 24 rising edges and only 23 falling edges during the CS low period. The final falling edge occurs approximately 100 μs after the CS line goes high.
After some testing, I modified the clock phase to “2nd Edge,” which successfully generates the CLK signal as I wanted. However, now it’s no longer writing the expected data to the slave device.
I’ve attached the following for reference:
- The code I’m using
HAL_StatusTypeDef ret;
int32_t wr_ret = (int32_t)EMBL_WRONGPARAMS;
SPI_HandleTypeDef *hPDev = (SPI_HandleTypeDef *)WRSPI_getPhysicalDevice(hSPI);
if (hPDev != NULL && pData != NULL && DataSize > 0){
WRSPI_setCSS(hSPI, false);
do {
ret = HAL_SPI_Transmit(hPDev, pData, DataSize, 1000);
} while (ret == HAL_BUSY);
if (ret != HAL_OK){
wr_ret = EMBL_ERROR;
}else {
wr_ret = EMBL_OK;
}
WRSPI_setCSS(hSPI, true);
}- A capture from the logic analyzer with the clock phase to “1nd Edge,”
- A capture from the logic analyzer with the clock phase to “2nd Edge,”
- My CubeMX configuration
I’d appreciate any guidance on what might be causing these issues or how to resolve them.
Thank you in advance!
