Hi,
I am currently working with the STM32F334 and STM32G474 microcontrollers, and I have a couple of technical questions that require deeper insight into how the HRTIM (High-Resolution Timer) operates in these devices.
Q1. Can HRTIM generate a high-resolution variable-frequency waveform?
From my own testing, it appears yes, but I would like to confirm this officially. To clarify what I mean: suppose I am designing a resonant converter operating at 1 MHz. In the STM32F334, the HRTIM supports an effective edge resolution of ~217 ps, equivalent to a virtual clock of 4.608 GHz. This means the period register value for 1 MHz would be 4.608GHz/ 1MHz = 4608. Now, if I reduce the period by just one count 4.608GHz / 4607 = 1000217MHz This implies a frequency resolution of ~217 Hz. However, if high-resolution control were not supported for the period register, the period would instead be based on the timer base clock 144 MHz / 143 = 1.006993MHz. That would mean a frequency step of ~6993 Hz, much coarser than in the high-resolution case. In my practical testing, the frequency resolution I observed matched the 217 Hz scenario, suggesting that HRTIM does indeed support high-resolution period updates, or at least, simulates them through sub-tick edge positioning. Can you confirm whether HRTIM truly supports high-resolution frequency adjustment through fractional edge interpolation of the period?
Q2. If a HRTIM compare register triggers an ADC conversion, does the trigger also maintain 217 ps resolution?
In the above scenario, if a compare register is configured to trigger an ADC start of conversion, does this signal also carry sub-nanosecond resolution (~217 ps), or is it internally synchronized with the 72 MHz system clock, losing the high-resolution timing? I understand that the ADC requires at least 1.5 cycles for sampling and 12.5 cycles for conversion, and that its internal operations are governed by the ADC clock. However, my question is about the precision of the triggering edge, particularly whether the start-of-conversion (SOC) signal benefits from the high-resolution HRTIM output. It seems to me that high-resolution triggering of the ADC may not have a significant impact, since regardless of the SOC precision, the end of the sampling phase is ultimately synchronized to the 72 MHz ADC clock.
