Issues with library of G431

[Tobe]

Hi, 

after spending already the half day, i finally found one problem of multiple:

https://github.com/STMicroelectronics/cmsis-device-g4/blob/master/Include/stm32g431xx.h
Line 1029 continues with wrong offset. Should be 18. Following are wrong too.

After fixing this error, i still cant get the DMA to work on ADC1. ADC2 works fine, so i guess i figured it out. What i think is, that there may be more mistakes?

EDIT:

Allthough the above is different than in the manual, and the debugview, that part seems to work. 

Is "DMA request MUX input" No. 5 really connected to ADC1?? (Manual page 426) The DMA just does not get triggered.

[KDJEM.1]

Hello @Tobe,

About the channel offset, as stm32g431 is a category 2 device (Table 1. STM32G4 Series memory density), there are only 12 DMAMUX instances instead of 16 (Table 90. DMAMUX instantiation).

For that, each six allocated to one of the two DMA controllers.

As the register-mapping layout is done on the basis of eight channels per DMA controller, there will be an offset of 8 bytes for the six higher instances:

DMAMUX1_Channel0 offset 0x0000
DMAMUX1_Channel1 offset 0x0004
DMAMUX1_Channel2 offset 0x0008
DMAMUX1_Channel3 offset 0x000C
DMAMUX1_Channel4 offset 0x0010
DMAMUX1_Channel5 offset 0x0014

// unused 0x0018//
// unused 0x001C//

DMAMUX1_Channel6 offset 0x0020
DMAMUX1_Channel7 offset 0x0024
DMAMUX1_Channel8 offset 0x0028
DMAMUX1_Channel9 offset 0x002C
DMAMUX1_Channel10 offset 0x0030
DMAMUX1_Channel11 offset 0x0034
// unused 0x0038//
// unused 0x003C//
Therefore, the macros defined in stm32g431xx.h are correct.

[waclawek.jan]

Hi @KDJEM.1 

I don't see any such offset mentioned in the primary documentation, i.e. the RM:

Can you please comment on this.

Btw. there are other STM32 with DMAMUX with similar "non-8-channel-per-DMA" scheme, so can you please comment on those, too.

JW

[KDJEM.1]

Hello @waclawek.jan,

Thank you for bringing this behavior to our attention.

I will check internally this issue between the reference manual and the driver. And, I will come back to you with details as soon as possible.

Thank you.

Kaouthar

[Tobe]

The debugger also shows the registers, that are not present. This is what me got into thinking, that the lib was wrong.

[KDJEM.1]

Hello @waclawek.jan and @Tobe, 

After check, Table 96. supports only DMAMUX register map and reset values for category 3 and category 4 devices.

A new table should be added in the coming revision to support DMAMUX register map and reset values for category 2 devices. This new table will be on line with https://github.com/STMicroelectronics/cmsis-device-g4/blob/master/Include/stm32g431xx.h 

- Addresses: 0x014 and 0x018 should be reserved
- DMAMUX_C8CR... DMAMUX_C13CR should be renamed to DMAMUX_C6CR... DMAMUX_C11CR
- Addresses: 0x038 and 0x03C should be reserved

->Btw. there are other STM32 with DMAMUX with similar "non-8-channel-per-DMA" scheme, so can you please comment on those, too

Could you please give an example of STM32MCUs with non-8-channel-per-DMA (supports DMA1 and DMA2 with non-8-channel?

- For example STM32WBx5 MCUs support 14 channels

DMAMUX is used with DMA1 and DMA2:
• DMAMUX channels 0 to 6 are connected to DMA1 channels 1 to 7
• DMAMUX channels 7 to 13 are connected to DMA2 channels 1 to 7

- STM32U031 MCUs support only DMA1 and 7 of DMAMUX output request.

- STM32MP1 supports 8-Channels-per-DMA

->The debugger also shows the registers, that are not present.

Thank you for bringing this issue to our attention. I reported internally.

Internal ticket number: 200921 (This is an internal tracking number and is not accessible or usable by customers) 

Thank you.

Kaouthar

[waclawek.jan]

Hi @KDJEM.1 ,

Thanks for the explanation.

Looking forward the updated 'G4 RM coming soon... ;)

So, if I understand it correctly, there's a bunch of STM32 with 7-channel DMA (besides 'WB5x, also, as you've shown above, the 'U7, and also 'L4+ and 'G0), where the DMAMUX channels are numbered continuously 0..6..N (as DMA1 appears to have always 7 channels before DMA2 is added with whatever number of channels), and no gap in DMAMUX addresses.

In this light, that 'G431 does have a gap in DMAMUX addresses but the numbering of channels is continuous, is IMO inconsistent, not only with other 'G4 but also with other families, and possible source of errors to those who migrate between STM32 models. This IMO makes the already mutually inconsistent DMAMUX/DMA channels numbering even somewhat worse.

But whatever confusing scheme ST has invented, please, pretty please, be meticulous in documenting it. For example, many STM32 RMs' DMAMUX chapters still don't have a clear and concise description of how the DMAMUX channels map to DMA channels(1-port)/streams(2-port). Please go through all related RMs and correct this.

JW

[KDJEM.1]

Hello @waclawek.jan ,

Thank you for your comments and feedback. I've reported it internally for checking.

Thank you.

Kaouthar