2019-01-18 12:04 AM
Hello, at this moment i'm investigating the possibilities of our current system and would like to know if the 2 Octo-spi peripherals can be used as legacy, normal SPI.
Solved! Go to Solution.
2019-01-23 02:52 AM
OctoSPI is master-only, byte-oriented, designed with memory accesses in mind. So, no problem for connection to memory devices and 'memory like' devices with single-line transfer via CS, SCKL, MOSI, MISO.
Some modes are not possible, e .g. data exchange (master and slave exchange data simultaneously). Read and write in a single transfer (meaning CS remains asserted) is somewhat restricted, as the OctoSPI operates either in read mode (only 4+4+4 bytes may be send to slave at begin of transfer, then only read) or write (arbitrary amount of bytes may be send to slave). No direct control of CS without reconfiguring CS pin to ordinary GPIO.
However, if you intend to use some 'exotic' slave device, I'd recommend to get a L4+-disco/nucleo board and verify that all transfer modes you need actually work as expected. The OctoSPI is rather new and there are some errata. I've used it only with memory both in 1- and 8-line modes so far, without problems.
2019-01-22 10:57 AM
"Investigating" should at least imply consulting the relevant docs, shouldn't it?
From RM 0432:
"OCTOSPI main features
• Three functional modes: indirect, status-polling, and memory-mapped
• Read and write support in memory-mapped mode
• Supports for single, dual, quad and octal communication
..."
and
"20.2 Efficient OctoSPI pin assignment with a full IO Matrix (before alternate function map)
OctoSPI IO Manager main features
• Supports up to two Single/Dual/Quad/Octal SPI Interfaces
• Supports up to 3 ports for pin assignment
• Fully programmable IO Matrix for pin assignment by function (data/control/clock)"
2019-01-22 09:55 PM
I Did read the documents, but at this point it is not clear if it is possible at all.
From DM00366449 it states:
but it doesn't make it clear for me if this can also be 5x normal spi, or if the 2x octospi are not configurable as normal spi.
2019-01-23 01:07 AM
So what's your definition/requirement list for a "normal SPI"? It you don't know or don't want to explain what features you actually need, then ... The RM explains the features and settings quite exhaustive.
There is obviously no register-compatibility, and certainly there are some modes of operation which are not possible for the OctoSPI (notably odd settings like 13-bit) but again: unless you don't say precisely what you expect ... "SPI" isn't any well-defined standard at all.
2019-01-23 01:39 AM
Alright, i understand what you were pointing at!
I should have given more information.
What i need is:
Mode = master
Data size = 8bit
Clock polarity = low
Clock phase = 1 edge
CRC = off
Slave select = software control
for the transfer i need DMA.
I need to transfer a changing amount of data.
2019-01-23 02:52 AM
OctoSPI is master-only, byte-oriented, designed with memory accesses in mind. So, no problem for connection to memory devices and 'memory like' devices with single-line transfer via CS, SCKL, MOSI, MISO.
Some modes are not possible, e .g. data exchange (master and slave exchange data simultaneously). Read and write in a single transfer (meaning CS remains asserted) is somewhat restricted, as the OctoSPI operates either in read mode (only 4+4+4 bytes may be send to slave at begin of transfer, then only read) or write (arbitrary amount of bytes may be send to slave). No direct control of CS without reconfiguring CS pin to ordinary GPIO.
However, if you intend to use some 'exotic' slave device, I'd recommend to get a L4+-disco/nucleo board and verify that all transfer modes you need actually work as expected. The OctoSPI is rather new and there are some errata. I've used it only with memory both in 1- and 8-line modes so far, without problems.
2019-01-24 12:06 AM
Thanks Andreas, i think this confirms what i was looking for. After testing a bit with the OctoSPI i cannot get it to work as "normal SPI".