Is it possible that samples are lost in DMA mode because of MCU BUS congestion?

[Georgy Moshkin]

Currently, I am facing an issue with synchronization between ADC and DAC.

ADC and DAC are both configured to use DMA1 in circular mode. ADC and DAC are both triggered by TIM4. I enable TIM4 right before main loop and observe perfect synchronization between DAC and ADC. If main loop contains arm_cfft_q31 function, I observe how ADC complete event is slowly becoming out of sync with DAC output. The same behavior is observed when I use UART to send sampled data using DMA mode. Interestingly, this effect became less prominent when I moved USART DMA TX from DMA1 to DMA2. Currently, I think that because of high ADC speed (18MHz in interleaved mode) concurrent access to MCU memory somehow disrupts DMA transfer from ADC. I made TIM4 to output 50% PWM signal and noticed that DAC is perfectly synchronized with PWM meander, and it is only ADC is going out of sync. May such effect be observed without any error flags raised? What is the best way to debug such a problem?

[KnarfB]

There is a DMA overrun flag in the ADC and a DMA underrun flag in the DAC and associated interrupts which you could use. There are also app notes like AN2548

Application note "Using the STM32F0/F1/F3/Gx/Lx Series DMA controller" giving insights into DMA bandwidth calculations and tuning.

hth

KnarfB

[Georgy Moshkin]

Thanks for your answer, I've dug through reference manual RM0433 and app notes AN2548 & AN5354 and found out that ADC clock was too high for LQFP variant, and that continuous mode was erroneously enabled. Disabling continuous mode solved the problem and sync is maintained between all channels regardless of USART DMA access and/or any computation.