Hello friends : )
I've recently tested the NUCLEO-G491RE board for an upcoming redesign.
Current design relies on quite tough interrupt latency so here is where I begun.
As I understand, with no FPU usage (in isr) (ASPEN + LSPEN = 0) one could expect up to 12 SYSCLK latency.
In this case 75ns at 160MHz which sounds pretty decent (today it's about 73ns).
I started off by creating two very similar interrupt services I intended to toggle between.
Each would pulse a output pin and trigger the other one:
Attributes: 'interrupt' + optimize("-O2")' + 'section(".RamFunc")' + 'aligned(8)' + 'naked'
static void onTimeStampEvent(void)
{
GPIOA->BSRR = 1<<12;
NVIC->ISPR[1] = 1<<(39-1*32); // USART3
GPIOA->BRR = 1<<12;
#ifdef NAKED
__ASM volatile ("BX LR":::);
#endif
return;
}
static void onReceiveEvent(void)
{
GPIOB->BSRR = 1<<14;
NVIC->ISPR[0] = 1<<(11-0*32); // DMA1_CH1
GPIOB->BRR = 1<<14;
#ifdef NAKED
__ASM volatile ("BX LR":::);
#endif
return;
}
In main the usual suspects:
- HAL and System initiation
- Peripheral initiation
- Setting up interrupts
Finally, the main loop:
u = 0;
while(1)
{
NVIC->ISPR[0] = 1<<(11-0*32); // DMA1_CH1
u++;
}
This works splendidly, sort of...
<PicoScope shot 1>
The total time for a complete round trip is about 381ns or 61 SYSCLK.
Variable "u" in main never changes from "0" suggesting expected continuous interrupts.
The thing is, would not tail-chaining occur?
Now I tried diversify priority levels, yellow being less important:
<PicoScope shot 2>
Priority in action, indeed, however now a round trip takes 562ns (90 SYSCLK).
Still no tail-chaining, and worse, lots of extra time for the same amount of work.
Where have I done wrong?
Any help appreciated = )
/Hen
