2017-01-24 01:25 PM
I asked a question earlier on how to generate n-Pulses from STM32 to drive a servo like interface ->
https://community.st.com/0D50X00009XkdsSSAR
, and it worked. This feature is available only on TIM1/8. Is there a novel way of interfacing 5 motors to one F7?I am trying to interface 5 Teknic Clearpath SDSK motors to STM32F7 Nucleo Dev Board. They are Brushless DC motors with a stepper like interface. The motor moves a set distance based on the number of pulses it receives. The speed is determined by the frequency of the pulses, like a stepper motor.
I can hook up the two motors to TIM1 and 8, and the rest with a feedback to counter,. DMA buffering won't work, as I rely on the pulses sent to determine the current position of the motor. I am just looking for a better solution here.
#stm32-pwm-timers #n-pulse2017-01-24 01:59 PM
Well there are several possibilities, for example pairing up two timers as master-slave and gating one from the other or using SPI with well-crafted data.
Neither is as simple and straighforward as the repetition-counter trick in timer and it's upon you to work out the details.
JW
2017-01-24 02:30 PM
Couldn't you one-shot from a interrupt, and count, is the rate likely to saturate the processor?
2017-01-24 03:39 PM
I need the pulses to be at a few 100 kHz frequency. I believe doing this for 5 (or 3) motors, along with a bunch of other things I want the processor to do, will saturate the processor.
2017-01-24 04:55 PM
How about using a $0.30 F0 part to control motor?
2017-01-24 05:05 PM
Its definitely an option. The overall system already has a couple of F7s and 5 F4s handling a lot of other things, so I am looking at solutions that would not add to the hardware complexity. If it becomes too complicated to handle it with firmware, hardware is the way to go. But at this time, I am exploring ways to control 5 of those motors with one F7.
2017-01-25 01:16 AM
How about using a $0.30 F0 part to control motor?
Or, how about a $0.03 74HC00 and less hassle with multiple programmable chips, using one timer as a 'carrier' and four other (or, with some care, four channels of one other timer) as 'gate'?
JW
2017-01-25 06:19 AM
All four motors have to be controlled at the same time, independent of each other. Otherwise, the motors have an enable line, that can be used to control them instead of using NAND gates.
2017-01-25 07:38 AM
All four motors have to be controlled at the same time, independent of each other.
Does this mean that they can't share the same source of pulses as 'carrier', being modulated either by an external NAND or using the enable inputs on the motors themselves? Does a latency of 1/few-100kHz between them make a significant difference?
JW
2017-01-25 02:26 PM
They can't share the same source.