I've always been a little unsure about how FIFO manages data transfer, so I ran a little experiment with a logic analyzer to understand it better, the result confused me even more.
I set up OCTOSPI to transmit 128 bytes to an external QSPI memory, with MDMA to handle the data transfer from DTCM to OCTOSPI data register.
- OCTOSPI FIFO Threshold = 16.
- MDMA uses Buffer Transfer mode with buffer transfer size = 16 bytes.
- MDMA buffer transfer is triggered by OCTOSPI FIFO threshold request.
- I enabled MDMA's Buffer Transfer Complete interrupt, for the sole purpose to toggle a pin in the ISR as an indicator that OCTOSPI FIFO has requested a buffer transfer.
Ok so with this setup I expect to see 8 buffer transfers (16 bytes each) by MDMA to move 128 bytes of data top OCTOSPI FIFO. Here's what the logic analyzer captured.
Each transition of the bottom trace (yellow) indicates an MDMA buffer transfer complete event. There are only 7! But all 128 bytes of data were successfully transmitted without error (I verified by reading them back). OCTOSPI fifo is 32 bytes deep, so maybe it pulled in 32 bytes in the first buffer transfer? But each buffer transfer should generate an interrupt, so there should still be 8 interrupt in total, no?
In the second experiment I increased the buffer transfer size to 64, OCTOSPI FIFO threshold is still 16.This time the buffer transfers occurred twice, as expected.
What I don't understand is how come MDMA was able to push 64 bytes into the 32 bytes deep FIFO? I guess there exist some sort of mechanism in the hardware that prevents FIFO being overrun by DMA transfer. With this in mind, I wonder, how should one determine the DMA buffer transfer size that yields the most efficient transfer to a comm peripherals with FIFO like OCTOSPI or SPI? And how does FIFO threshold come into the equation?
