About HWidj.2

HWidj.2 · 2022-01-11

As per RM0468, STM32H72x and STM32H73x chips have 192 KB of SRAM in the D1 domain that is 'sharable' between ITCM and AXI SRAM, ie. it can be allocated as ITCM or AXI SRAM with 64KB granularity,It is known that SRAMs in D1 (or any other domain for th...

HWidj.2 · 2021-09-23

I've always been a little unsure about how FIFO manages data transfer, so I ran a little experiment with a logic analyzer to understand it better, the result confused me even more.I set up OCTOSPI to transmit 128 bytes to an external QSPI memory, wit...

HWidj.2 · 2021-08-28

I'm configuring I2C4 as a slave receiver, using interrupt method. I noticed that when the I2C master (another MCU) sends the slave address, I2C4 detects an address match and sets the ADDR flag in the I2C4->ISR register. What baffles me is that at thi...

HWidj.2 · 2021-08-15

Reference Manual for STM32H72xxx/73xxx (RM0468), section 2.6, says that the embedded bootloader can be accessed via I2C1, I2C2, I2C3, I2C4 and SPI1, SPI2, SPI3, SPI4, however AN2606 only lists I2C1, I2C2, I2C3 and SPI, SPI3 as the working I2C and SPI...

HWidj.2 · 2021-07-22

Definition of I2C5 is missing from the STM32H723.svd file found in STM32CubeIDE 1.6.1 installation directory.Is this a mistake or by design? Because of this I can't access I2C5 control registers in the debugger.

HWidj.2 · 2022-01-11

Right after posting the question I stumbled open AN4891 which has a very detailed block diagram (page 10). Turns out the shareable D1 SRAM is dual ported, with one dedicated bus directly connected to the TCM bus, so seems like the answer is yes it wi...

HWidj.2 · 2021-08-21

Sorry, I have only had the time now to look at this issue again. This turned out to be my fault. I've missed the note on the Reference Manual (RM0468) which states that the MCO source selection and prescaler selection should be made before enabling t...

HWidj.2 · 2021-08-17

Thanks for the clarification.

HWidj.2 · 2021-07-22

Thanks!I noticed CubeIDE 1.7.0 is now available, downloaded and installed it and found the H723 SVD file has been updated and I2C5 definition is now present.

HWidj.2 · 2021-06-11

That's what I thought, thank you.

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Sharable D1 SRAMs in the more recent H7 chips

Interaction between peripheral's FIFO and MDMA transfer size

I2C (slave mode) behavior at beginning of transfer

Bootloader information discrepancy

STM32H723 SVD file incomplete

Re: Sharable D1 SRAMs in the more recent H7 chips

Re: High jitter on MCO output?

Re: Bootloader information discrepancy

Re: STM32H723 SVD file incomplete

Re: SAI or SPI clock requirement as I2S slave