In theory, you can use all 26 bit of the STM32U MDF in the CIC stage. In practice, I recommend to stay < 25 bit to avoid artifacts and saturation.

[_andreas]

Wrapping is inherent in the structure of a CIC, but as long as it does not occur "too often", it works just fine. The offset is applied after the CIC stage, it does not have a relevant influence.

[_andreas]

The MDF result is stored left aligned int32_t, the lower 8bits are always empty. Hence the max amplitude is +2147483392. Note that the SCALE stage has different gains.

[_andreas]

@Gwenole BROCHARD​ 

My test code on PC looks like this:

// downsample: drop D values after integrator section, then comb
// https://www.dsprelated.com/showarticle/1337.php
// the CIC uses weight * <IC> elements
// delay lines hold one element for each <IC> element of the CIC
 
int32_t intDelay[weight];
int32_t combDelay[weight];
memset(intDelay, 0, sizeof(intDelay));
memset(combDelay, 0, sizeof(combDelay));
 
unsigned j = 0;
unsigned combCnt = 0;
double cicGain = pow(downsample, weight);
 
for (unsigned i = 0; i < NSIZE; i++)
{
    int32_t x = in[i][0];
    x <<= cicShift;
    for (unsigned k = 0; k < weight; k++) {
        x += intDelay[k]; // sum to element in delay line
        intDelay[k] = x;  // store new sum in delay line
    }
    // downsampler
    combCnt++;
    if (combCnt >= downsample) {
        // comb section
        combCnt = 0;
        for (unsigned k = 0; k < weight; k++) {
            int32_t ov = combDelay[k]; // get old value from delay line
            combDelay[k] = x; // add new value to delay line
            x -= ov; // substract old value from new value
        }
        in[j++][0] = x / cicGain / (1 << cicShift);
    }
}

with in is the input (and output) data,

I want to run an FFT on it, so it's a two dimensional array of doubles. I only use the real part here. NSIZE is obviously the number of elements in the array.

weight is the CIC order, downsample is the decimatio ratio, cicShift is used to simulate the limited number of bits in the MDF CIC stage. cicGain has a correspondence to the MDF SCALE stage.

[_andreas]

@Gwenole BROCHARD​ was so kind to simulate it and could not reproduce it - using the exact same setup. Since mathematics works, this claim is wrong: There must be differences in the setup.

Possible sources are:

1. The ST simulation does not match the chip (my simulation code as posted here gives the result of the chip)
2. The simulation test harness does not use the same width - the Reference manual gives only results for ADC with 12bit resolution, so this is a possibility.
3. The simulated ADC has a difference in the top values (the datasheet mentions 0.2V from rail as maximum possible output for buffered DAC, but my board reaches rail). If the simulation uses the values from the datasheet, then there is a possible gap.
4. Last but not least (for now) there may be a difference in the sampling rate, which I did not mention so far. I'm clocking the ADC1 from a PLL with 5.632 MHz, 5 samples ts, 14 bit resolution. This results in a sampling rate of 256 kHz. The input signal has a frequency of ~ 200Hz.