2010-06-07 07:01 AM
2011-05-17 04:54 AM
Hi Thomas,
First, it depends on which device you are using: (connectivity line (STM32F105/7) or high-density line (STM32F103/5)). Second, are you sure that you have Fs = 48 KHz ? could you please tell us the PLL dividers/multipliers and the I2S dividers (I2SDIV and I2SODD) you are using ? for example: for high density line, when system is running on 72MHz, you should have I2SDIV = 3 and I2SODD = 0... It would be nice if you share the piece of code where you configure the I2S ... Cheers.2011-05-17 04:54 AM
2011-05-17 04:54 AM
2011-05-17 04:54 AM
Check the frequency of the external oscillator.
2011-05-17 04:54 AM
I'm running this eval board:
http://www.st.com/stonline/products/literature/um/15867.pdf which has an on-board 16Mhz crystal so could that be the case that I get twice the MLCK frequency using the clock-divider settings presented? If I change: RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); to: RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_3); I get the right clock (12mhz) but doesn't that affect the core frequency of the ARM core too (which I don't want as I need the full 72mhz)? Can I somehow probe the clock signal the goes to the ARM core? Hope you can reserve a little more time with this problem - I have the feeling we are pretty close solving this! Thanks Thomas2011-05-17 04:54 AM
Hi,
''I have the feeling we are pretty close solving this!'' Yes indeed :) I think the issue is this define: ''HSE_VALUE'' or ''HSE_Value'' (depends on the version of firmware library you are using) in the file stm32f10x.h in folder CMSIS/CM3/DeviceSupport/ST/STM32F10x (if you have the latest version). You should set this define to the right value of your external crystal because the default value is 25MHz while you have 16MHz ... Just look for this define and modify it and everything will be OK :) Thanks Clive for the hint :) Good luck.2011-05-17 04:54 AM
Divide the input to the PLL by 2
RCC_PLLConfig(RCC_PLLSource_HSE_Div2, RCC_PLLMul_9); PLLout = (16 MHz / 2) * 9 = 72 MHz Wow the forum is putting answers out of order. Great job Microsoft.2011-05-17 04:54 AM
Damn it :)
I still don't reach the 12.8Mhz ..I misread the scope output. The SYSCLK is 72MHZ is and this goes directly to the I2S interface so the clock decimation has to be done there. I haven't succeeded making this work. Clive, by doing what you suggest the SYSCLK changes to 36MHZ which I can't live with. But it does give the right I2S clock Any suggestions? Best Regards Thomas Yeah the posting order is wrong here2011-05-17 04:54 AM
Are you sure you are using HSE? and that it is 16 MHz
RCC_PLLSource_HSE_Div2 and a multiplier of 9 should give a 72 MHz SYSCLK for a 16 MHz source. If it is not something is very wrong. My boards use 8MHz HSE/HSI, so can't check it myself. If you use RCC_PLLSource_HSI_Div2 you will get 36 MHz Damn this forum is screwy, why exactly did ST migrate from the old one that worked so nicely?