Posted on May 17, 2011 at 13:54Hi Clive I do get the right SYSCLK and using the clock divider I can make it 36Mhz. The problem is a the I2S master clock output doesn't show to be 12.8Mhz (48e3*256) but 25Mhz. I suspect that this has to do with the I...
Posted on May 17, 2011 at 13:54Damn it I still don't reach the 12.8Mhz ..I misread the scope output. The SYSCLK is 72MHZ is and this goes directly to the I2S interface so the clock decimation has to be done there. I haven't succeeded making this ...
Posted on May 17, 2011 at 13:54I'm running this eval board: http://www.st.com/stonline/products/literature/um/15867.pdf which has an on-board 16Mhz crystal so could that be the case that I get twice the MLCK frequency using the clock-divider setting...
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