2010-06-07 07:01 AM
2011-05-17 04:54 AM
Hi Clive
I do get the right SYSCLK and using the clock divider I can make it 36Mhz. The problem is a the I2S master clock output doesn't show to be 12.8Mhz (48e3*256) but 25Mhz. I suspect that this has to do with the I2S configuration. I understand if this thread it getting boring :) Thanks again Thomas2011-05-17 04:54 AM
I think it comes back to chikos' hint.
You really need to ensure that HSE_Value is correct (stm32f10x_conf), and that if you are importing the libraries as a precompiled .LIB file, you had better recompile them and rebuild the library with the correct value. Unsure, then select HSE as your clock source instead of the PLL, and use RCC_GetClocksFreq() to see what value the library is using (RCC_Clocks->SYSCLK_Frequency)2011-05-17 04:54 AM
I work with STM32F107RC and codec CS42L51. I configure and set up all for I2S2 communication, but MCLK signal on PC6 pin is only present when I send data over I2S2 in interrupt subroutine. I need MCLK signal all time.
Is MCLK only present when you send data?
Dragan
2011-05-17 04:54 AM
That's how the I2S works on STM32: MCLK and all I2S clocks are generated only when you send data.
I used the CS43L22 and I did simply send dummy data when I have no real data to send (note: using DMA is much more performant than using interrupt). I also tried without sending dummy data and it works as well (you just have to set mute before end of streamand reset it again before restarting a new stream). Third solution: you can use an external clock for both I2S and CS42L51 and use I2S in slave mode. Anyway, have a look on the USB audio speaker which is using the audio codec and the I2S:http://www.st.com/stonline/products/support/micro/files/um0424.zip
2011-05-17 04:54 AM
Thanks, Chikos
I will try with first and second solution...
Best regards,
Dragan