I2C Clock line held low by stm32 and not recovered

[ArunyaS]

Hi,

Currently, I am facing an issue with STM32 MCU I2C communication.

I have facing an I2C timed-out error on the host side while communicating with the MCU I2C continuously.

The I2C clock line was held low when the issue occurred, I wasn't able to communicate further with the I2C line.

I've attached an image for you to look over.

The I2C line will recover after resetting the MCU.

This issue only occurs in long-run continuous communication in the I2C line.

Configuration:

MCU: STM32L476JGY6TR

SLAVE I2C: I2C-2

SPEED: 400KHZ(Fast Mode)

INPUT FREQ: 48Mhz - MSI Clock

I2C lines are pulled up with a 4.7K ohm resistor to a 1.8V source

Kindly help to solve this.

Thank you!

[TDK]

Looks like your logic analyzer and your signal are out of sync. Perhaps show from the start of the signal. This looks very much like an ACK pulse:

The solution to recover from a stuck SCL is the following:

• Reinitialize SCL pin as a GPIO open-drain output.
• Starting from the high state, toggle the SCL pin 18 times to get 9 pulses at 100 or 400 kHz.
• Reinitialize SCL as I2C.

[ArunyaS]

Hi @TDK ,

   I can communicate with the I2C line after reinitialising the GPIO pin. But, I want to know why the SCL line held low and got an "I2C transfer Timed out" issue.

and also want to know, why this will occur in the long run Continous communication.

Note:

I noticed the slave I2C held the clock line low.

Thanks.

[TDK]

Looks like the slave and master get descynchronzed. This could be due to a code bug (most likely) or a glitch on the line. If you save enough data on the logic analyzer you could pinpoint where this happens exactly. If it's always in the same spot, probably a code bug.

There are some oddities in the I2C peripheral as well. It is probably not a silicon issue, but that is also a possibility. Consult the errata sheet for your chip.