i2c clock; how to config ?

[placidity.master_gmail.com]

in RM0008 Rev 21

page 775

Bits 5:0 FREQ[5:0]: Peripheral clock frequency

the description of the frequency divider is extremely unclear. there is no formula for where the input is, how it is divided, where the output is. what if I want to set strictly 50kHz for iic ?

once again, to understand the documentation, you need to switch to the "fortune teller" mode.

and then there is a separate I2C Clock control register (I2C_CCR).

the concept of fPCLK1 is used there, but where did it come from?

"let's guess."

"the maximum frequency is limited by the maximum APB frequency and cannot exceed

50 MHz"

but the description of APB1 says a maximum of 36 MHz.

how did 36 turn into 50 ?

the name of the PE bit gives a special thrill;

parity error ?

no, it's the peripherals to turn on.

in all documentation, all allow bits start with EN;

which is kind of logical, to allow a bit of such and such. but suddenly, in one place, the logic of the document is forgotten and we get PE instead of the logical EN_Peripheral;

[Foued_KH]

Hello @placidity.master_gmail.com​,

The maximum APB frequency :50 MHz.

The maximum peripheral clock frequency : 36 MHz

This condition is respected :

==> Higher than 36 MHz not allowed.

Foued.

[placidity.master_gmail.com]

and the line above says about 50 MHz, almost in one place two contradictory installations.

[Foued_KH]

The frequency is limited by 50MHz ( max APB frequency) but cannot exceed the 36MHz.

[placidity.master_gmail.com]

don’t care about these frequencies, I’ve been more than a week, I can’t see at least 1 byte at the output, according to the oscilloscope, the output pulls the resistor down 1 time and then silence.

here is the config,

void      configure_iic_1   ( void )

{

   //   Bit 21 I2C1EN: I2C1 clock enable

   RCC->APB1ENR   |=   1 << 21;   // DEBUG

   I2C1->CR1   |=   I2C_CR1_SWRST;   //   reset

   I2C1->CR2 |= 36;   //DEBUG

   I2C1->TRISE = 9;

   set_iic_1_ccr (   2000 );   // DEBUG TODO

   //set_iic_1_cr_1_bit ( I2C_CR1_BIT_NUM_PE ) ;      //   Peripheral enable

   I2C1->CR1 |= 1;

}

and here is a snippet that is called 1 time per second

   configure_iic_1();

   set_iic_1_cr_1_bit ( I2C_CR1_BIT_NUM_START ) ;      //   Peripheral enable

   wait_10_CPU_clock_cycles();

   iic_1_write_data ( 0xAA );

I have not yet seen a more confusing fragment in the documentation, the i2c standard itself is simple as a log, but ST managed to make the periphery and documentation "not edible"

[Piranha]

> maximum APB frequency :36 MHz

> 50MHz ( max APB frequency)

Your usefulness is negative! Can you put a two and two together and give a clear and reliable answer instead of these thoughtless blurts?