STM32H7R7: How to setup XSPI for external nor flash AT25XE321D

[Leo2Ruan]

Hi,

The external nor flash AT25XE321D is 32Mbits, support quad IO/XIP spi operation, max. 133MHz Freq. Std. JEDEC/SFDP. It is connected to STM32H7R7Z8J6 with with XSPI1 port-1 interface.

I am using MX v6.116.1 to setup project for my board. By IDE v2.0.0, the project 'Boot' works from internal flash but it is failed to run 'Appli' from external AT25XE321D. And the project 'ExtMemLoader' is successfully built and deployed:

• File copied successfully under STM32CubeProgrammer.
• File copied successfully under STM32CubeIDE

I tried STM32CubeProgrammer v2.21.0 to program the AT25XE321D with using the ExtMemLoader.stldr I just built, but failed too. "Error: Mass erase operation failed." See attached log for more logs.

Back to my settings in MX:

1) 100MHz XSPI1 clock source

2) XSPI1 settings and GPIOs

There 4 memory types available and no 'custom' option. I pick the 'Macronix' as it is most close to AT25XE321D.

3) ExtMemLoader settings

I also go through followings but did not help me to solve the problem:

• AN5050: Getting started with Octo-SPI, Hexadeca-SPI, and XSPI interfaceson STM32 MCUs
• https://community.st.com/t5/stm32-mcus/how-to-create-an-external-flash-loader-for-an-stm32h7rs/ta-p/742005
• https://community.st.com/t5/stm32-mcus/integrating-and-debugging-external-memory-on-stm32-mcus-part-2/ta-p/865238

Can any one give me hand, thanks in advance!

[KDJEM.1]

Hello @Leo2Ruan ;

To choose the memory type you need to refer to memory datasheet and check the data ordering.

Micron mode, D0/D1 ordering in DTR 8-data-bit mode.
Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol
Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode.

Also, I recommend you to take a look at this wiki article Getting started with External memory Manager and External memory loader - stm32mcu and get inspired to configure your project.

This article introduces the External Memory Manager and External Memory Loader in order to:

• Provide an API that allows access to all types of memory.
• Launch an application stored in an external memory.
• Generate an External memory loader file

I hope this help you.

Thank you.

Kaouthar

[Leo2Ruan]

@KDJEM.1Thanks for reply!

With debugging on my board, I find the problem takes place at exact the reading of SFDP header.

AT25XE321D documents the SFDP read is supported by command 0x5A follows 1-1-1 transfer format. That is 1 byte command + 3 bytes address + 1 byte dummy + data on SO. This is match with the function 'SFDP_GetHeader()' MX generated. The code PHY_LINK_1S1S1S is used to get SFDP header. But the signature value returned is 0x5300460044005000 while expected value 0x50444653 ('P','D','F','S'). Well, each signature byte follows ox00. With 1-1-1 SDR format, I think at least AT25XE pins are correctly connected with STM32H7 XSPI.

case PHY_LINK_1S1D1D:
case PHY_LINK_1S2S2S:
case PHY_LINK_1S1S2S:
case PHY_LINK_1S1S1S:
 {
 s_commandbase.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
 s_commandbase.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
 s_commandbase.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
 s_commandbase.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
 s_commandbase.AddressWidth = HAL_XSPI_ADDRESS_24_BITS;
 s_commandbase.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE;
 s_commandbase.DataMode = HAL_XSPI_DATA_1_LINE;
 s_commandbase.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE;
 s_commandbase.DummyCycles = 8;
 s_commandbase.DQSMode = HAL_XSPI_DQS_DISABLE;
break;
 }

I don't understand how this could be. So I tested the PHY_LINK_1S1S1S, PHY_LINK_1S1S2S, PHY_LINK_1S2S2S, PHY_LINK_1S1D1D by putting it within table_config[] in function SFDP_GetHeader(). All got same wrong signature 0x00460053. And I also tested through with memory type: Micron, Macronix, PA RAM and Macronix RAM. Problem is still there.

From AT25XE321D datasheet, I believe the SFDP data is sent without 0x00 in between because the complete 'S','F','D','P' are presented in FIFO. I suspect the STM32H7 somehow pad 0x00 for each byte in FIFO even if the data DTR is disabled already. Any idea? 

Thank you!

Leo Ruan

[Leo2Ruan · Accepted solution]

The problem is fixed by setting 'memory-mode' from enable to disable in MX. This generated diff code as below:

diff --git a/Appli/Core/Src/main.c b/Appli/Core/Src/main.c
index d23a96c..595628d 100644
--- a/Appli/Core/Src/main.c
+++ b/Appli/Core/Src/main.c
@@ -367,7 +367,7 @@ static void MX_XSPI1_Init(void)
/* XSPI1 parameter configuration*/
hxspi1.Instance = XSPI1;
hxspi1.Init.FifoThresholdByte = 4;
- hxspi1.Init.MemoryMode = HAL_XSPI_DUAL_MEM;
+ hxspi1.Init.MemoryMode = HAL_XSPI_SINGLE_MEM;
hxspi1.Init.MemoryType = HAL_XSPI_MEMTYPE_MACRONIX;
hxspi1.Init.MemorySize = HAL_XSPI_SIZE_32MB;
hxspi1.Init.ChipSelectHighTimeCycle = 3;

[KDJEM.1]

Hello @Leo2Ruan ;

Glad to know that the issue is solved.

Thank you for sharing the solution.

Kaouthar

[Leo2Ruan]

@KDJEM.1Follow wiki article Getting started with External memory Manager and External memory loader - stm32mcu you posted, I double check my settings for CLOCK, XSPI, MPU, middlewares and SBS in MX, and update following setting:

1) The middleware 'EXTMEM_MANAGER_APPLI' not mentioned in the article but presents in MX v6.16.1. In my understanding, the application inherits the XSPI-P1 setting from Boot made and running in XIP (memory map) mode. So the EXTMEM_MANAGER_APPLI shall be inactivated.

2) Although the nor flash work in 133MHz, I still activate the HSLV for XPIM in SBS.

3) Key: After checking the AT25XE datasheet, it supports 1-1-4 and 1-4-4 quad operations in STR mode only. In MX, which memory type shall be used?

Thanks!

Leo Ruan

[Leo2Ruan]

Let's close the topic with conclusion: MX can't generate code to support the nor flash other than 4-4-4 STR mode.

Some options:

- Skip the SFDP phase and hardcode nor flash specific parameters in driver.

- Patch the code MX generated to support nor flash for 1-4-4 or 1-1-4 mode.

- Customize driver.

I prefer the first.