2022-07-13 09:28 AM
2022-07-13 09:56 PM
One channel has only one register for comparison, so there is no trivial solution to this task. You can combine two channels for one output using asymmetric or combined PWM modes (see ref. manaul or search the forum). This limits you to two outputs for one timer, say TIM1. For 3 output channels, you may use two synchronized timers (e.g. TIM1 and TIM8).
With one timer only, it might be feasible using timer interrupts and change/update timer settings at each interrupt for the next part of the PWMs.
DMA could also help. One solution is a timer driven cyclic DMA, copying a buffer to a GPIO BSRR register which can genarate any pulse train.
hth
KnarfB
2022-07-14 09:47 AM
> You can combine two channels for one output using asymmetric or combined PWM modes
> (see ref. manual or search the forum).
> This limits you to two outputs for one timer,
You can use:
ph1: TIM1_CH1 alone
ph2: TIM1_CH2 combined with TIM1_CH5, by setting TIM1_CCR5.GC5C2 (This combination may not not available in all STM32 models, but it's present in 'F723, so I believe it's also in 'F730. Check in RM.)
ph3: TIM1_CH3 combined with TIM1_CH4.
JW