I am trying to optimize my code on a STM32F303, because it seems to be abnormally slow. Is it possible the CPU is running at a lower clock speed?

[JBell.5]

I've got a function that's literally only a switch statement, which is compiling to a compare, a branch, and a TBB instruction. Yet it's taking 48 cycles (as measured by TIM2->CNT before and after). How can this be? This is insanely slow. I've found the same with many other functions -- bizarre things, like a short byte-by-byte memcpy taking ~20 cycles per byte?! It's only three instructions in a loop...

By the clock diagram, I would think TIM2 should be running at the same speed, and running faster is not possible, so it's not the timer being wrong. I've tried putting the function in CCM RAM -- there is no meaningful difference. What could explain this?

[MM..1]

as measured by TIM2->CNT

you dont show how you measure but good practice is place tested code to for example 10000 loops and measure tim on start to end

reading tim cost too cycles... loop jumps and decrement is next cycles... usw

[JBell.5]

Reading TIM costs 4, I checked. This isn't a loop. I've run it many times and it's consistently 48.

[TDK]

Speed up the CPU isn't going to change the number of cycles it takes (generally). Likely your timing scheme is just flawed and is capturing a significant amount of overhead in addition to the event you're measuring. Examine and show assembly code to ensure it's as good as it can get. Subtract off known overhead from reading registers.

[waclawek.jan]

> Examine and show assembly code

+1 - all of it, from first TIM2_CNT read to the second.

Also, to start from a known good point, avoid *any* initialization code (SystemInit() and similar garbage). If you do, post content of all registers it touched (mainly RCC and FLASH).

> I've tried putting the function in CCM RAM -- there is no meaningful difference.

Are you sure you've run it from the RAM?

JW

PS. You did not single-step the code while measuring performance, did you?

[S.Ma]

I would try to use the debug cycle counter core register to make sure the timer currently used may have wrong clock freq value, only cortex M0s miss this debug feature. Then take snapshots and disable interrupy between start amd stop snapshots to make sure.