HSI or HSE ?

[placidity.master_gmail.com]

HSI or HSE ?

carefully read the pictures

[waclawek.jan]

The HSI/2 divider is fixed. See PLLSRC description.

PLLXTPRE is a copy of 0th bit of PREDIV (for historical reasons) - it's quite clearly written in description of both fields.

JW

[placidity.master_gmail.com]

in the picture, HSE is divided once, but the text shows that the second divisor by 2 is hidden somewhere, but it is not in the scheme. but there is an HSI divider that, judging by the bits, can be configured.

[Tesla DeLorean]

No, the register here reflects two copies of the same bit.

The HSI is divided by TWO, always,as it comes from a pulse generator, and doesn't have the prerequisite 50/50 duty.

For the purpose of setting the PLL assume the HSI/2 input is always 4 MHz

[placidity.master_gmail.com]

thanks

here is a piece of text that I overlooked:

This bit is the same as the LSB of PREDIV in Clock configuration register 2

(RCC_CFGR2) (for compatibility with other STM32 products)