HSI I2C Accuracy

[tomm5771]

I am trying to use the 16 MHz HSI as the clock source for I2C. When I set up the I2C_TIMINGR bits for 100kbps I2C, everything works fine. When I try to set up for 400kbps, it still works, but the timing is not 400kbps. Does the accuracy of the HSI decrease when using I2C at higher speeds? The I2C speed comes out to around 300 kbps when using the HSI. I am setting the I2C_TIMINGR register so that the SCLH and SCLL are both 0x13 (19 decimal) because if you plug this into the formula provided, it comes out to have both the high and low part of the I2C clock to 1.25 usec. SCLH is the high part of the clock, SCLL is the low part of the clock.

Formulas are tSCLH = (SCLH + 1) x tPRESC and tSCLL  = (SCLL + 1) x tPRESC. tPRESC is 62.5 nsec. I am setting both SCLH and SCLL to 0x13 and am expecting to get 1.25 usec. That is not what it is coming out to when I look at I2C traffic on a scope. 

[TDK]

> Take a conservative estimate of rise time as being 1/20 of the clock period.

I'm not sure how familiar you are with I2C. It seems like you're taking what you would expect with SPI and applying it here. Take a look at I2C timing traces on the web and you'll see that 1/20th of the clock period is in no way conservative. Here's two relatively slow ones and one that looks better:

Which is why I say seeing the traces would be informative.

Clock frequency on I2C is not exact as the STM32 needs to wait for edges to happen (as the I2C spec requires). The reference manual even states this. It's not an open loop system like UART or SPI.

[BarryWhit]

You're right, I assumed it's (at least electrically) similar to what I know and apparently that's not the case.