HSI, HSE, LSI, LSE and clock nonsense

Rami Rosenbaum (old) · ‎2017-02-22

Posted on February 22, 2017 at 22:05

Hi,

I'm working on a stm32F101CBT6.

The board has a 16 MHz HSE (connected to PD0.PD1) and a 32.768 KHz LSE (connected to PC14/PC15).

The board will use SPI1, SPI2, USART1, USART2, I2C1 and a few GPIOs.

I've worked with ST microcontrollers before, but never had to configure the clocks, so I'll be probably asking some naive questions, please be gentle... I do know that external oscillators are much more precise than the internal ones.

When creating a new project with CubeMX, it defaults to HSI and LSI.

If I enable MCO (PA8) and listen with an analyzer - I get 8 MHz. That seems correct.

1. If I configure the clock configuration, via CubeMX, to use HSE with 16 MHz (the board schema says 16 MHz) - I see on MCO 16.67 MHz. Is that correct?

2. What is the logic, the aim of playing with the PLL, and - should I use it?

My common sense says I should aim for the highest frequency in the SYSCLK and the buses.

I've attached my CubeMX project file, if it helps.

Thanks

#hse-hsi-pll-rcc

Tesla DeLorean · ‎2017-02-22

Posted on February 22, 2017 at 22:53

The PLL uses an input clock, and an internal VCO (voltage controlled oscillator, pulse generator), where the feedback loop from the frequency comparator tunes the VCO to a desired frequency. This allows you to create a much faster clock, usually a 2x the desired speed which is divided by two to get a nice 50/50 duty signal to clock the chip. So from your 8 or 16 MHz input we can clock at 72 MHz on some STM32F1 series parts.

You'll need to decide how fast you need to clock to get things done, and say supply a USB peripheral with 48 MHz, or clock the APB x16 faster than the USART rate you want supported.

16.67 MHz seems a bit on the fast side of something claim to be 16 MHz, check the circuit/components AS BUILT.

If this is some board on the market, provide some cite, circuit diagram, or perhaps a clearly focused picture of the crystal markings. I have insufficient context to know 'is this correct', but it doesn't sound ideal. If the HSE is actually 16.67 MHz this is something that needs to get plugged into the tools, and reflected in the HSE_VALUE used to do maths for the SYSCLK and USART baud rates.

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View solution in original post

Tesla DeLorean · ‎2017-02-22

Posted on February 22, 2017 at 22:53

The PLL uses an input clock, and an internal VCO (voltage controlled oscillator, pulse generator), where the feedback loop from the frequency comparator tunes the VCO to a desired frequency. This allows you to create a much faster clock, usually a 2x the desired speed which is divided by two to get a nice 50/50 duty signal to clock the chip. So from your 8 or 16 MHz input we can clock at 72 MHz on some STM32F1 series parts.

You'll need to decide how fast you need to clock to get things done, and say supply a USB peripheral with 48 MHz, or clock the APB x16 faster than the USART rate you want supported.

16.67 MHz seems a bit on the fast side of something claim to be 16 MHz, check the circuit/components AS BUILT.

If this is some board on the market, provide some cite, circuit diagram, or perhaps a clearly focused picture of the crystal markings. I have insufficient context to know 'is this correct', but it doesn't sound ideal. If the HSE is actually 16.67 MHz this is something that needs to get plugged into the tools, and reflected in the HSE_VALUE used to do maths for the SYSCLK and USART baud rates.

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

waclawek.jan · ‎2017-02-23

Posted on February 23, 2017 at 11:03

Make a closeup photo of the crystal so that its marking is visible and post it here.

JW

Rami Rosenbaum (old) · ‎2017-02-23

Posted on February 23, 2017 at 10:09

Thanks, exactly the answer I hoped for, something to point me to the right direction.

The board is custom. The company, who designed and created the original SW, has 'vanished', so I only have the schema and original binaries.

I'll continue from here, do some homework, and return if needed.

Thanks again

Rami Rosenbaum (old) · ‎2017-02-23

Posted on February 23, 2017 at 11:05

I may end up using the internal clocks.

What are the dangers of using the internal clocks?

I'm not using the RTC, and UART bursts are not more than 300 bytes (with checksum).

i2c and SPI have a 'relative' clock (excuse me for my unprofessional English).

And - is there a reason not to use the highest clock-rate possible? 36MHz in my case.

Thanks

Rami Rosenbaum (old) · ‎2017-02-23

Posted on February 23, 2017 at 11:23

I've attached a pic of the Xtal: '0 AMM2 H5C', I think

________________

Attachments :

FSM-HSE.JPG : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006Hyr7&d=%2Fa%2F0X0000000bDX%2FzDahVx6HAXUHH.io_1_InwYQhNCNZV7d_HKJToDBw5o&asPdf=false

waclawek.jan · ‎2017-02-23

Posted on February 23, 2017 at 12:24

This is a hummm. There are 16.66/16.67MHz crystals around, but this one is specifically marked as 16.0 (yes I've seen misleading marking on crystals e.g. numbers after MHz frequency denoting precision) but here, should the '.0' mean anything else than fraction of MHz, it would be a very wicked thing.

Yes it might be a mislabelled part, this happens, but rare.

How exactly do you measure the frequency on MCO?

JW

Rami Rosenbaum (old) · ‎2017-02-23

Posted on February 23, 2017 at 12:31

With a 'Saleae Logic 8' logic analyzer, which reaches a speed of 100 MS/s

Jan Waclawek · ‎2017-02-23

Posted on February 23, 2017 at 12:54

How many MCO periods?

100MHz converts to 10ns uncertainty, one period at 16MHz is 60ns.

JW

Rami Rosenbaum (old) · ‎2017-02-23

Posted on February 23, 2017 at 13:27

I'm capturing over a second.

The period is 40ns+20ns = 60ns, frequency = 16.67MHz