HSI/2 before PLLSRC in STM32F030xC ?

[Peter M]

Posted on January 26, 2018 at 18:50

Hi,

I have a problem with the PLLSRC of a STM32F030RC : to obtain 24MHz for the sysclk I have to use PLLMUL @ x6 with HSI (8MHz) but 6x8 = 48MHz ?

If I output the sysclk on a MCO pin (with no div) I have actually 24MHz.

After use of SystemCoreClockUpdate() from system_stm32f0xx.c the variable SystemCoreClock equals to 48000000 and my call to SysTick_Config(SystemCoreClock/1000) gives a wrong systick frequency ( 2 x too slow, the actuel sysclock is 24000000).

In the reference manual RM0360 at the figure 11 I see no div /2 between HSI and PLLSRC for my STM32F030xC.

But the behaviour 

seems like in the figure 10, with a /2 ....

Where is the mistake ?

Thanks

Peter

[Peter M]

Posted on June 28, 2018 at 21:47

I confirm :

DEV_ID = 0x442

DIV_ID = 0x6

REV_ID = 0x1000

[waclawek.jan]

Posted on June 29, 2018 at 12:38

Okay and now look at the IDs in RM0091 (MCU device ID code chapter).

The 'F030 are the same silicon as the other 'F0xx (several of them), with less testing (e.g. lower temperature range) and cut down features (either disabled by some way or simply present but not guaranteed to work (untested)).

I find it very unlikely the arrangement of HSI divider would be configured in some way in the production to make it working differently in 'F030xC than in 'F091; I find it more likely that RM0360 is defective.

JW

[Peter M]

Ok Jan, you was right....

Hey ST, look in your RM0360 page 102, RCC_CFGR : "Bit 15 Reserved, must be kept at reset value."

And then look in your stm32f030xc.h line 3120 :

"#define RCC_CFGR_PLLSRC_HSI_PREDIV        (0x00008000U)         /*!< HSI/PREDIV clock selected as PLL entry clock source */"