Hello everyone,
I am generating PWM signals using the HRTIM module. Specifically, I am using Timer D to generate a PWM signal along with its complementary signal. This signal is always in phase with the master counter, setting at the timer period and resetting at the half-period.
Similarly, Timer C also generates a PWM signal, but unlike Timer D, it allows phase shifting relative to Timer D.
The issue arises when I try to apply a phase shift step greater than 50% of the period. In this case, instead of obtaining the desired output (shown in blue), I get an unwanted signal (shown in black). Oviously this behavior is only in the phase shift transient.
From what I understand, it seems that the set in timer period, marked in purple, is being skipped. However, I am not sure if the skipped moment could be instead the one shown in blue. Or even if this is the origin of the problem.
However, if I set the PWM to trigger at CMP1 = 0 of Timer D instead of PRD, and reset at CMP2=0.5*PRD, I don’t observe this issue. The problem is that I don’t want to use this approach because HRTIM is not designed to handle compare values smaller than 3 periods of the HRTIM clock, which in my case is CMP<24. Although in practice seems to work fine.
Does anyone have any suggestions on how to resolve this while keeping the desired configuration? It is important for the application, since i have more PWM outputs, to keep phase shifting in master timer compares, and duty cycle (which is practically always constant at 50%) in the subtimers compares.
Here i put the real signals passing from a phase of 70% to a phase of 30%, giving a phase step of 60%>50%. White lines are the desired output. Blue PWM is timer C and green is timer D.
Or in this case passing from 10 to 80% (step of 70%)
Kind regards,
Pau Moreno
