HRTIM PWM transients greater than a period

PMoreno · ‎2025-02-15

Hello everyone,

I am generating PWM signals using the HRTIM module. Specifically, I am using Timer D to generate a PWM signal along with its complementary signal. This signal is always in phase with the master counter, setting at the timer period and resetting at the half-period.

Similarly, Timer C also generates a PWM signal, but unlike Timer D, it allows phase shifting relative to Timer D.

The issue arises when I try to apply a phase shift step greater than 50% of the period. In this case, instead of obtaining the desired output (shown in blue), I get an unwanted signal (shown in black). Oviously this behavior is only in the phase shift transient.

From what I understand, it seems that the set in timer period, marked in purple, is being skipped. However, I am not sure if the skipped moment could be instead the one shown in blue. Or even if this is the origin of the problem.

However, if I set the PWM to trigger at CMP1 = 0 of Timer D instead of PRD, and reset at CMP2=0.5*PRD, I don’t observe this issue. The problem is that I don’t want to use this approach because HRTIM is not designed to handle compare values smaller than 3 periods of the HRTIM clock, which in my case is CMP<24. Although in practice seems to work fine.

Does anyone have any suggestions on how to resolve this while keeping the desired configuration? It is important for the application, since i have more PWM outputs, to keep phase shifting in master timer compares, and duty cycle (which is practically always constant at 50%) in the subtimers compares.

Here i put the real signals passing from a phase of 70% to a phase of 30%, giving a phase step of 60%>50%. White lines are the desired output. Blue PWM is timer C and green is timer D.

Or in this case passing from 10 to 80% (step of 70%)

Kind regards,

Pau Moreno

PMoreno · ‎2025-02-26

To solve the duty higher that 1 instead of doing the set in Timer period event, the PWM is set at CMP=0. Probably if I do the set with a master compare, it will work also.

On the other hand, the error that i had when i phase shift exactly 0.5, was that last PWM reset event and new PWM set event were happening at the same time, so set event was ignored. To solve this, I do the set with CMP3 and reset with CMP1, becasue the higher the CMP, the more priority it has. So when reset and set is done in less than 3 periods of the HRTIM clock, reset is ignored and set is applied.

View solution in original post

ST_Sophia · ‎2025-02-20

Dear User,

Based on information you provided, I think that such behavior is indeed what is expected by the programming: When current shift is less than 50%, and a new shift programming occurs, if the preload option is not applied, and the counter of HRTIM_TIMC did not reach yet the new reset value (shift more than 50%), then both resets will be applied on the HRTIM_TIMC during the same period of Master Timer leading to the short transient period of TIMC.

Have you enabled the preload option (PEEN) in Master Timer? This will help to make the update of value of CMP2 of Master Timer conditioned by the roll-over of master counter, so only one value of TIMC shift will be applied.

I hope this help, please let me know if additional information is required.

Best regards,

PMoreno · ‎2025-02-20

The Preload in Master Timer is enabled and still happens. But I don't understant why if I change the set of the PWM to CMP=0, instead of the period, it works.

ST_Sophia · ‎2025-02-21

I'm not sure that the counter waveform (on which we see blue and purple marks) are showing the exact behavior of the timer counter.

First, the CMP > 3 is indeed the requirement, but the CMP=0 is also a valid usecase: "Null duty cycle exception case" in RM of hrtim,

Do you have an IOC file to share ? I need to access to additional configurations.

Check please without preload on Master also, this will lead to 2 immediate reset cause on the same cycle, so HRTIM C counter could reset, and SET applied.

PMoreno · ‎2025-02-25

Now I have the set in CMP1=0 and reset in CMP2=HALFPERIOD. With this seems to not generate duty cycles greater than 1 period.


Mcu.UserConstants=HALFPERIOD_MASTER,5230;PERIOD_MASTER,10460;INIT_MODULATION,2615
HRTIM1.ADCTrigger1_Source1=HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3
HRTIM1.ADCTrigger3_Source1=HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4
HRTIM1.ADCTrigger_Id1=HRTIM_ADCTRIGGER_1
HRTIM1.ADCTrigger_Id10=__NULL
HRTIM1.ADCTrigger_Id2=__NULL
HRTIM1.ADCTrigger_Id3=HRTIM_ADCTRIGGER_3
HRTIM1.ADCTrigger_Id4=__NULL
HRTIM1.ADCTrigger_Id5=HRTIM_ADCTRIGGER_5
HRTIM1.ADCTrigger_Id6=__NULL
HRTIM1.ADCTrigger_Id7=__NULL
HRTIM1.ADCTrigger_Id8=__NULL
HRTIM1.ADCTrigger_Id9=__NULL
HRTIM1.CaptureUnit1-Output_TA1TA2=__NULL
HRTIM1.CompareUnit1-MasterTimer=HRTIM_COMPAREUNIT_1
HRTIM1.CompareUnit1-Output_TA1TA2=HRTIM_COMPAREUNIT_1
HRTIM1.CompareUnit1-Output_TB1TB2=HRTIM_COMPAREUNIT_1
HRTIM1.CompareUnit1-Output_TC1TC2=HRTIM_COMPAREUNIT_1
HRTIM1.CompareUnit1-Output_TD1TD2=HRTIM_COMPAREUNIT_1
HRTIM1.CompareUnit1-Output_TE1TE2=HRTIM_COMPAREUNIT_1
HRTIM1.CompareUnit1-Output_TF1TF2=HRTIM_COMPAREUNIT_1
HRTIM1.CompareUnit2-MasterTimer=HRTIM_COMPAREUNIT_2
HRTIM1.CompareUnit2-Output_TA1TA2=HRTIM_COMPAREUNIT_2
HRTIM1.CompareUnit2-Output_TB1TB2=HRTIM_COMPAREUNIT_2
HRTIM1.CompareUnit2-Output_TC1TC2=HRTIM_COMPAREUNIT_2
HRTIM1.CompareUnit2-Output_TD1TD2=HRTIM_COMPAREUNIT_2
HRTIM1.CompareUnit2-Output_TE1TE2=HRTIM_COMPAREUNIT_2
HRTIM1.CompareUnit2-Output_TF1TF2=HRTIM_COMPAREUNIT_2
HRTIM1.CompareUnit3-MasterTimer=HRTIM_COMPAREUNIT_3
HRTIM1.CompareUnit3-Output_TA1TA2=__NULL
HRTIM1.CompareUnit3-Output_TB1TB2=__NULL
HRTIM1.CompareUnit3-Output_TC1TC2=__NULL
HRTIM1.CompareUnit3-Output_TD1TD2=HRTIM_COMPAREUNIT_3
HRTIM1.CompareUnit3-Output_TE1TE2=__NULL
HRTIM1.CompareUnit3-Output_TF1TF2=__NULL
HRTIM1.CompareUnit4-MasterTimer=HRTIM_COMPAREUNIT_4
HRTIM1.CompareUnit4-Output_TA1TA2=__NULL
HRTIM1.CompareUnit4-Output_TB1TB2=__NULL
HRTIM1.CompareUnit4-Output_TE1TE2=__NULL
HRTIM1.CompareUnit4-Output_TF1TF2=__NULL
HRTIM1.CompareValue1-MasterTimer=PERIOD_MASTER
HRTIM1.CompareValue1-Output_TA1TA2=0
HRTIM1.CompareValue1-Output_TB1TB2=0
HRTIM1.CompareValue1-Output_TC1TC2=0
HRTIM1.CompareValue1-Output_TD1TD2=0
HRTIM1.CompareValue1-Output_TE1TE2=0
HRTIM1.CompareValue1-Output_TF1TF2=0
HRTIM1.CompareValue2-MasterTimer=PERIOD_MASTER
HRTIM1.CompareValue2-Output_TA1TA2=HALFPERIOD_MASTER
HRTIM1.CompareValue2-Output_TB1TB2=HALFPERIOD_MASTER
HRTIM1.CompareValue2-Output_TC1TC2=HALFPERIOD_MASTER
HRTIM1.CompareValue2-Output_TD1TD2=HALFPERIOD_MASTER
HRTIM1.CompareValue2-Output_TE1TE2=HALFPERIOD_MASTER
HRTIM1.CompareValue2-Output_TF1TF2=HALFPERIOD_MASTER
HRTIM1.CompareValue3-MasterTimer=PERIOD_MASTER
HRTIM1.CompareValue3-Output_TD1TD2=7845
HRTIM1.CompareValue4-MasterTimer=INIT_MODULATION
HRTIM1.DeadTimeInsertion-Output_TA1TA2=HRTIM_TIMDEADTIMEINSERTION_ENABLED
HRTIM1.DeadTimeInsertion-Output_TB1TB2=HRTIM_TIMDEADTIMEINSERTION_ENABLED
HRTIM1.DeadTimeInsertion-Output_TC1TC2=HRTIM_TIMDEADTIMEINSERTION_ENABLED
HRTIM1.DeadTimeInsertion-Output_TD1TD2=HRTIM_TIMDEADTIMEINSERTION_ENABLED
HRTIM1.DeadTimeInsertion-Output_TE1TE2=HRTIM_TIMDEADTIMEINSERTION_ENABLED
HRTIM1.DeadTimeInsertion-Output_TF1TF2=HRTIM_TIMDEADTIMEINSERTION_ENABLED
HRTIM1.FallingValue-Output_TC1TC2=34
HRTIM1.FallingValue-Output_TD1TD2=34
HRTIM1.FaultEnable_Source1-Output_TA1TA2=HRTIM_TIMFAULTENABLE_NONE
HRTIM1.FaultEnable_Source1-Output_TB1TB2=HRTIM_TIMFAULTENABLE_NONE
HRTIM1.FaultEnable_Source1-Output_TC1TC2=HRTIM_TIMFAULTENABLE_NONE
HRTIM1.FaultEnable_Source1-Output_TD1TD2=HRTIM_TIMFAULTENABLE_NONE
HRTIM1.FaultEnable_Source2-Output_TA1TA2=HRTIM_TIMFAULTENABLE_NONE
HRTIM1.FaultEnable_Source2-Output_TB1TB2=HRTIM_TIMFAULTENABLE_NONE
HRTIM1.FaultEnable_Source2-Output_TC1TC2=HRTIM_TIMFAULTENABLE_NONE
HRTIM1.FaultEnable_Source2-Output_TD1TD2=HRTIM_TIMFAULTENABLE_NONE
HRTIM1.FaultLevel1-Output_TA1TA2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.FaultLevel1-Output_TB1TB2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.FaultLevel1-Output_TC1TC2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.FaultLevel1-Output_TD1TD2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.FaultLevel1-Output_TE1TE2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.FaultLevel1-Output_TF1TF2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.FaultLevel2-Output_TA1TA2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.FaultLevel2-Output_TB1TB2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.FaultLevel2-Output_TC1TC2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.FaultLevel2-Output_TD1TD2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.FaultLevel2-Output_TE1TE2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.FaultLevel2-Output_TF1TF2=HRTIM_OUTPUTFAULTLEVEL_INACTIVE
HRTIM1.Fault_Line1=__NULL
HRTIM1.GreaterCMP1_TA=HRTIM_TIMERGTCMP1_EQUAL
HRTIM1.GreaterCMP1_TB=HRTIM_TIMERGTCMP1_EQUAL
HRTIM1.GreaterCMP1_TE=HRTIM_TIMERGTCMP1_EQUAL
HRTIM1.GreaterCMP1_TF=HRTIM_TIMERGTCMP1_EQUAL
HRTIM1.HRTIMInterruptResquests1=HRTIM_IT_NONE
HRTIM1.HRTIMInterruptResquests2=HRTIM_IT_NONE
HRTIM1.IPParameters=Periode_MASTER,DeadTimeInsertion-Output_TA1TA2,NumberResetTrigger-Output_TA1TA2,ResetTrigger1-Output_TA1TA2,NumberSetSource1-Output_TA1TA2,SetOutput1_Source1-Output_TA1TA2,NumberResetSource1-Output_TA1TA2,CompareUnit1-Output_TA1TA2,ResetOutput1_Source1-Output_TA1TA2,Periode_TA,Periode_TB,DeadTimeInsertion-Output_TB1TB2,NumberResetTrigger-Output_TB1TB2,CompareUnit1-MasterTimer,CompareValue1-MasterTimer,CompareUnit2-MasterTimer,CompareUnit3-MasterTimer,ResetTrigger1-Output_TB1TB2,CompareUnit1-Output_TB1TB2,CompareValue1-Output_TB1TB2,NumberSetSource1-Output_TB1TB2,SetOutput1_Source1-Output_TB1TB2,NumberResetSource1-Output_TB1TB2,ResetOutput1_Source1-Output_TB1TB2,Periode_TC,DeadTimeInsertion-Output_TC1TC2,NumberResetTrigger-Output_TC1TC2,ResetTrigger1-Output_TC1TC2,CompareUnit1-Output_TC1TC2,CompareValue1-Output_TC1TC2,RisingValue-Output_TC1TC2,FallingValue-Output_TC1TC2,NumberSetSource1-Output_TC1TC2,SetOutput1_Source1-Output_TC1TC2,NumberResetSource1-Output_TC1TC2,ResetOutput1_Source1-Output_TC1TC2,Periode_TD,DeadTimeInsertion-Output_TD1TD2,NumberResetTrigger-Output_TD1TD2,ResetTrigger1-Output_TD1TD2,CompareUnit1-Output_TD1TD2,CompareValue1-Output_TD1TD2,RisingValue-Output_TD1TD2,FallingValue-Output_TD1TD2,NumberSetSource1-Output_TD1TD2,NumberResetSource1-Output_TD1TD2,SetOutput1_Source1-Output_TD1TD2,ResetOutput1_Source1-Output_TD1TD2,ADCTrigger_Id1,NumberADCTriggerSource1,postscaler1,ADCTrigger1_Source1,CompareValue1-Output_TA1TA2,GreaterCMP1_TA,CompareValue2-MasterTimer,CompareValue3-MasterTimer,CompareUnit4-MasterTimer,CompareValue4-MasterTimer,CompareUnit2-Output_TA1TA2,CompareUnit3-Output_TA1TA2,CompareUnit4-Output_TA1TA2,PreloadEnable-Output_TB1TB2,CompareUnit2-Output_TB1TB2,ADCTrigger_Id3,PreloadEnable-MasterTimer,NumberInterruptRequests_Master-MasterTimer,InterruptRequests1_Master,GreaterCMP1_TB,PrescalerDead-Output_TC1TC2,PrescalerDead-Output_TD1TD2,RepetitionUpdate-MasterTimer,PrescalerRatio_TA,PrescalerRatio_MASTER,PrescalerRatio_TB,PrescalerRatio_TC,PrescalerRatio_TD,NumberFaultEnable-Output_TA1TA2,FaultEnable_Source1-Output_TA1TA2,FaultLevel1-Output_TA1TA2,FaultLevel2-Output_TA1TA2,NumberFaultEnable-Output_TB1TB2,FaultEnable_Source1-Output_TB1TB2,FaultLevel1-Output_TB1TB2,FaultLevel2-Output_TB1TB2,NumberFaultEnable-Output_TC1TC2,FaultEnable_Source1-Output_TC1TC2,FaultLevel1-Output_TC1TC2,FaultLevel2-Output_TC1TC2,NumberFaultEnable-Output_TD1TD2,FaultEnable_Source1-Output_TD1TD2,FaultLevel1-Output_TD1TD2,FaultLevel2-Output_TD1TD2,HRTIMInterruptResquests2,HRTIMInterruptResquests1,FaultEnable_Source2-Output_TA1TA2,FaultEnable_Source2-Output_TB1TB2,FaultEnable_Source2-Output_TC1TC2,FaultEnable_Source2-Output_TD1TD2,CaptureUnit1-Output_TA1TA2,ADCTrigger_Id2,PrescalerRatio_TE,Periode_TE,NumberFaultEnable-Output_TE1TE2,DeadTimeInsertion-Output_TE1TE2,NumberResetTrigger-Output_TE1TE2,NumberUpdateTrigger-Output_TE1TE2,NumberSetSource1-Output_TE1TE2,SetOutput1_Source1-Output_TE1TE2,CompareUnit1-Output_TE1TE2,CompareValue1-Output_TE1TE2,NumberResetSource1-Output_TE1TE2,ResetOutput1_Source1-Output_TE1TE2,ResetTrigger1-Output_TE1TE2,GreaterCMP1_TE,FaultLevel1-Output_TE1TE2,FaultLevel2-Output_TE1TE2,PrescalerRatio_TF,Periode_TF,NumberFaultEnable-Output_TF1TF2,DeadTimeInsertion-Output_TF1TF2,NumberResetTrigger-Output_TF1TF2,ResetTrigger1-Output_TF1TF2,CompareUnit1-Output_TF1TF2,CompareValue1-Output_TF1TF2,GreaterCMP1_TF,NumberSetSource1-Output_TF1TF2,SetOutput1_Source1-Output_TF1TF2,NumberResetSource1-Output_TF1TF2,ResetOutput1_Source1-Output_TF1TF2,FaultLevel1-Output_TF1TF2,FaultLevel2-Output_TF1TF2,CompareValue2-Output_TA1TA2,CompareUnit3-Output_TB1TB2,CompareValue2-Output_TB1TB2,CompareUnit2-Output_TC1TC2,CompareUnit2-Output_TD1TD2,CompareUnit2-Output_TE1TE2,CompareValue2-Output_TE1TE2,CompareUnit2-Output_TF1TF2,CompareValue2-Output_TF1TF2,Polarity1-Output_TB1TB2,Polarity1-Output_TE1TE2,Polarity2-Output_TE1TE2,Polarity2-Output_TB1TB2,CompareUnit3-Output_TF1TF2,CompareUnit4-Output_TF1TF2,NumberSetSource2_TF,NumberResetSource2_TF,CompareUnit3-Output_TE1TE2,CompareUnit4-Output_TE1TE2,NumberSetSource2_TE,NumberResetSource2_TE,CompareUnit3-Output_TC1TC2,NumberSetSource2_TA,CompareUnit4-Output_TB1TB2,NumberSetSource2_TB,NumberResetSource2_TB,PrescalerDead-Output_TB1TB2,PrescalerDead-Output_TA1TA2,PrescalerDead-Output_TE1TE2,PrescalerDead-Output_TF1TF2,Fault_Line1,NumberADCTriggerSource3,ADCTrigger3_Source1,postscaler3,ADCTrigger_Id4,ADCTrigger_Id5,Source_ADCTrigger5,postscaler5,CompareValue2-Output_TC1TC2,CompareValue2-Output_TD1TD2,CompareUnit3-Output_TD1TD2,ADCTrigger_Id6,ADCTrigger_Id7,ADCTrigger_Id8,ADCTrigger_Id9,ADCTrigger_Id10,CompareValue3-Output_TD1TD2
HRTIM1.IPParametersWithoutCheck=CompareValue3-Output_TA1TA2
HRTIM1.InterruptRequests1_Master=HRTIM_MASTER_IT_MCMP4
HRTIM1.NumberADCTriggerSource1=1
HRTIM1.NumberADCTriggerSource3=1
HRTIM1.NumberFaultEnable-Output_TA1TA2=2
HRTIM1.NumberFaultEnable-Output_TB1TB2=2
HRTIM1.NumberFaultEnable-Output_TC1TC2=2
HRTIM1.NumberFaultEnable-Output_TD1TD2=2
HRTIM1.NumberFaultEnable-Output_TE1TE2=2
HRTIM1.NumberFaultEnable-Output_TF1TF2=2
HRTIM1.NumberInterruptRequests_Master-MasterTimer=1
HRTIM1.NumberResetSource1-Output_TA1TA2=1
HRTIM1.NumberResetSource1-Output_TB1TB2=1
HRTIM1.NumberResetSource1-Output_TC1TC2=1
HRTIM1.NumberResetSource1-Output_TD1TD2=1
HRTIM1.NumberResetSource1-Output_TE1TE2=1
HRTIM1.NumberResetSource1-Output_TF1TF2=1
HRTIM1.NumberResetSource2_TB=0
HRTIM1.NumberResetSource2_TE=0
HRTIM1.NumberResetSource2_TF=0
HRTIM1.NumberResetTrigger-Output_TA1TA2=1
HRTIM1.NumberResetTrigger-Output_TB1TB2=1
HRTIM1.NumberResetTrigger-Output_TC1TC2=1
HRTIM1.NumberResetTrigger-Output_TD1TD2=1
HRTIM1.NumberResetTrigger-Output_TE1TE2=1
HRTIM1.NumberResetTrigger-Output_TF1TF2=1
HRTIM1.NumberSetSource1-Output_TA1TA2=1
HRTIM1.NumberSetSource1-Output_TB1TB2=1
HRTIM1.NumberSetSource1-Output_TC1TC2=1
HRTIM1.NumberSetSource1-Output_TD1TD2=1
HRTIM1.NumberSetSource1-Output_TE1TE2=1
HRTIM1.NumberSetSource1-Output_TF1TF2=1
HRTIM1.NumberSetSource2_TA=0
HRTIM1.NumberSetSource2_TB=0
HRTIM1.NumberSetSource2_TE=0
HRTIM1.NumberSetSource2_TF=0
HRTIM1.NumberUpdateTrigger-Output_TE1TE2=0
HRTIM1.Periode_MASTER=PERIOD_MASTER
HRTIM1.Periode_TA=PERIOD_MASTER
HRTIM1.Periode_TB=PERIOD_MASTER
HRTIM1.Periode_TC=PERIOD_MASTER
HRTIM1.Periode_TD=PERIOD_MASTER
HRTIM1.Periode_TE=PERIOD_MASTER
HRTIM1.Periode_TF=PERIOD_MASTER
HRTIM1.Polarity1-Output_TB1TB2=HRTIM_OUTPUTPOLARITY_HIGH
HRTIM1.Polarity1-Output_TE1TE2=HRTIM_OUTPUTPOLARITY_HIGH
HRTIM1.Polarity2-Output_TB1TB2=HRTIM_OUTPUTPOLARITY_HIGH
HRTIM1.Polarity2-Output_TE1TE2=HRTIM_OUTPUTPOLARITY_HIGH
HRTIM1.PreloadEnable-MasterTimer=HRTIM_PRELOAD_ENABLED
HRTIM1.PreloadEnable-Output_TB1TB2=HRTIM_PRELOAD_DISABLED
HRTIM1.PrescalerDead-Output_TA1TA2=HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4
HRTIM1.PrescalerDead-Output_TB1TB2=HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4
HRTIM1.PrescalerDead-Output_TC1TC2=HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4
HRTIM1.PrescalerDead-Output_TD1TD2=HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4
HRTIM1.PrescalerDead-Output_TE1TE2=HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4
HRTIM1.PrescalerDead-Output_TF1TF2=HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4
HRTIM1.PrescalerRatio_MASTER=HRTIM_PRESCALERRATIO_MUL8
HRTIM1.PrescalerRatio_TA=HRTIM_PRESCALERRATIO_MUL8
HRTIM1.PrescalerRatio_TB=HRTIM_PRESCALERRATIO_MUL8
HRTIM1.PrescalerRatio_TC=HRTIM_PRESCALERRATIO_MUL8
HRTIM1.PrescalerRatio_TD=HRTIM_PRESCALERRATIO_MUL8
HRTIM1.PrescalerRatio_TE=HRTIM_PRESCALERRATIO_MUL8
HRTIM1.PrescalerRatio_TF=HRTIM_PRESCALERRATIO_MUL8
HRTIM1.RepetitionUpdate-MasterTimer=HRTIM_UPDATEONREPETITION_ENABLED
HRTIM1.ResetOutput1_Source1-Output_TA1TA2=HRTIM_OUTPUTRESET_TIMCMP2
HRTIM1.ResetOutput1_Source1-Output_TB1TB2=HRTIM_OUTPUTRESET_TIMCMP2
HRTIM1.ResetOutput1_Source1-Output_TC1TC2=HRTIM_OUTPUTRESET_TIMCMP2
HRTIM1.ResetOutput1_Source1-Output_TD1TD2=HRTIM_OUTPUTRESET_TIMCMP2
HRTIM1.ResetOutput1_Source1-Output_TE1TE2=HRTIM_OUTPUTRESET_TIMCMP2
HRTIM1.ResetOutput1_Source1-Output_TF1TF2=HRTIM_OUTPUTRESET_TIMCMP2
HRTIM1.ResetTrigger1-Output_TA1TA2=HRTIM_TIMRESETTRIGGER_MASTER_CMP3
HRTIM1.ResetTrigger1-Output_TB1TB2=HRTIM_TIMRESETTRIGGER_MASTER_CMP3
HRTIM1.ResetTrigger1-Output_TC1TC2=HRTIM_TIMRESETTRIGGER_MASTER_CMP2
HRTIM1.ResetTrigger1-Output_TD1TD2=HRTIM_TIMRESETTRIGGER_MASTER_PER
HRTIM1.ResetTrigger1-Output_TE1TE2=HRTIM_TIMRESETTRIGGER_MASTER_CMP1
HRTIM1.ResetTrigger1-Output_TF1TF2=HRTIM_TIMRESETTRIGGER_MASTER_CMP1
HRTIM1.RisingValue-Output_TC1TC2=34
HRTIM1.RisingValue-Output_TD1TD2=34
HRTIM1.SetOutput1_Source1-Output_TA1TA2=HRTIM_OUTPUTSET_TIMCMP1
HRTIM1.SetOutput1_Source1-Output_TB1TB2=HRTIM_OUTPUTSET_TIMCMP1
HRTIM1.SetOutput1_Source1-Output_TC1TC2=HRTIM_OUTPUTSET_TIMCMP1
HRTIM1.SetOutput1_Source1-Output_TD1TD2=HRTIM_OUTPUTSET_TIMCMP1
HRTIM1.SetOutput1_Source1-Output_TE1TE2=HRTIM_OUTPUTSET_TIMCMP1
HRTIM1.SetOutput1_Source1-Output_TF1TF2=HRTIM_OUTPUTSET_TIMCMP1
HRTIM1.Source_ADCTrigger5=HRTIM_ADCTRIGGEREVENT579_MASTER_PERIOD
HRTIM1.postscaler1=5
HRTIM1.postscaler3=0x0
HRTIM1.postscaler5=30

But now I'm encountering another issue. In this scenario, I transition from a phase where TIMC = 1, TIMD = Ref, TIMF = 1, and TIMA = 1 to a phase where TIMC = 0.5, TIMD = Ref, TIMF = 0.54, and TIMA = 0.04. Considering TIM D analog to master timer because is in phase, when TIMC shifts from 0 to 0.5, since the reset of the PWM is at HALFPERIOD, the set and reset is done at the same time, so set is ignored. This delay means that the changes in TIMC and TIMF are applied one period apart, leading to an unintended voltage during that period, which significantly increases the current.

Javier1 · ‎2025-02-25

I dont know if related, but there is a very annoying "minimum effective Counter Register value" for HRTIM compare registers.

https://community.st.com/t5/stm32-mcus-products/hrtim-has-minimum-cr-values/td-p/775378

This made my PWM to not trigger with CR<32, and show always high/low cycle.

hit me up in https://www.linkedin.com/in/javiermu%C3%B1oz/

PMoreno · ‎2025-02-25

I take this effect into account skipping CR between 0 and that minimum, as I see you did it. The effect of doing this is minimal on the phase shift. I am more worried with phase shift transients that can generate unwanted voltage references during 1 period.

PMoreno · ‎2025-02-26

To solve the duty higher that 1 instead of doing the set in Timer period event, the PWM is set at CMP=0. Probably if I do the set with a master compare, it will work also.

On the other hand, the error that i had when i phase shift exactly 0.5, was that last PWM reset event and new PWM set event were happening at the same time, so set event was ignored. To solve this, I do the set with CMP3 and reset with CMP1, becasue the higher the CMP, the more priority it has. So when reset and set is done in less than 3 periods of the HRTIM clock, reset is ignored and set is applied.