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How to use printf/scanf in both cores using SWO?

Steven Keeter
Associate III

I have the M7 core running and printing debug messages to the IAR Workbench terminal, and also have the M4 doing something similar. My probem is that I get a hard fault in the M4 core if the its printtf messages are included in the build. If I don't use the printf() functions within the M7 code then the M4 is ok and printd its messages. So, can both cores share the SWO line when using printf debug statements?

Steven Keeter
Associate III

Update: According to IAR

"Unfortunately SWO and printf via SWO is not supported with a multi-core project.

The Debug Log window will show:

Warning: Trace mode 'None' is forced for multi-core debugging.

Warning: Power and SWO trace are not possible in multi-core debugging.

The above means that no SWO functions work - including printf via SWO.

Note that using printf via Semihosting may also not work very well with multi-core,

since the CPU is stopped and started frequently when using it.

The recommended, and most common solution is to overwrite the function __write so that it writes stdout output to UART instead.

See chapter "__write" and example code in Help > C/C++ Development Guide.

The template file can be found in <EWARM>\arm\src\lib\file\write.c"

However, I was able to get around this issue by using the HSEM ( hardware semaphore ) to ensure only one core executes a printf() at a time. In doing this the SWO output to the IAR Workbench terminal works fine. If you don't make them mutually exclusive then you will get a hard fault. I imagine that IAR's uart recommendation will suffer the same fate if sharing a common uart, and using separate uarts are probably fine to use simultaneously.

I think you'd probably need to have one core responsible for output, and queue lines to text for dispatch, perhaps with a tag indicating the source MCU, otherwise lines will likely all garble together.

If you only need output, perhaps find some unused UARTs just wire up the TX side, and service with a chaining DMA IRQ

Interplay with dual cores is probably going to be a challenge if not allowed to occur real-time.

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Hey, do you have add extra instruction or something to switch the ITM multiplexer when a core is transmitting via SWO line ? I was unable to make SWO printf on either core, just using UART1 and HSEM to share it between cores. But it is slow and sluggish. Remember how good was the ITM SWO on H753, and i think if you have one of those quality debuggers with the huge FPGA inside, the SWO pin can stream out at 100 Mbps. Thank you!

Steven Keeter
Associate III

Hi MONKA, If you're still trying to use the SWO for printf() messages in both cores, just check the project properties to ensure the library configurations for semihosting are selected for both cores. I am now using a uart instead...complications in switching from the DISCO board to NUCLEO board and not able to cconnect my I-jet to the SWD port anymore.

Could you please post your code for this? I'd love to see an example of this working.