How to use OCREF_CLR (COMP1 AS OCREF_CLR),I found it not work correctly.(STM32G431C8t6).When comp1 is in blanking mode,the pwm is low(it should be high).

[waclawek.jan]

> When comp1 is in blanking mode,the pwm is low(it should be high)

Why do you think it should be high?

Read out and check/post content of TIM registers.

JW

[立张.1]

I set the INP voltage of comp1 higher than the INM voltage of comp1. The pwm is high (PWM1 mode,CNT<CCRT)

[立张.1]

void TIM3Init(void)

{

TIM3GpioInit();

RCC -> APB1ENR1 |= 1 << 1;

TIM3 -> CR1 = 0;

TIM3 -> CR1 |= 1 << 7;//Auto-reload preload enable

TIM3 -> CR1 |= 1 << 3;//one pulse 

TIM3 -> CR1 |= 1 << 2;//Only counter overflow/underflow generates an update interrupt or DMA request if enabled

TIM3 -> CR2 |= 4 << 4;//CCR1 as TRGO

TIM3 -> SMCR |= 3 << 4;//tim4_trgo       

TIM3 -> SMCR |= 1 << 16 ;//RESET && enable MODE

 /////////////////////////////////////////////////////////

TIM3 -> CCMR1 |= 7 << 4;//ccr1 < CNT inactive//PWM2

TIM3 -> CCMR1 |= 1 << 3;

TIM3 -> CCMR1 |= 6 << 12;//ccr2 < CNT active//PWM1

TIM3 -> CCMR1 |= 1 << 11;

////////////////////////////////////////////////////////////

TIM3 -> CCMR1 |= 1 << 15; //20230506 clr en

  TIM3 -> CCMR2 |= 6 << 4; //CCR3 < CNT active//PWM1

TIM3 ->CCMR2 |=1<<3;  //20230525

TIM3 -> CCMR2 |= 7 << 12;//ccr4 < CNT inactive//PWM2

TIM3 -> CCMR2 |= 1 << 11;

TIM3 -> CCER |= 1 << 12;//CC4 enable

TIM3 -> CCER |= 1 << 4;//CC2 enable

TIM3 -> CCER |= 1 << 8;//20230505 CC3 enable

TIM3 -> CCER |= 1 ;//CC1 enable

TIM3 -> PSC = 0;

TIM3 -> ARR = 1700 ;

TIM3 -> CCR1 = 850;      //main.c

TIM3 -> CCR2 = 850; //20230505

TIM3 ->CCR3 = 25;      //blanking source of COMP1

TIM3 -> CCR4 = 850; //

TIM3 -> CNT = 0;

TIM3 -> SMCR &= ~((unsigned int )1 << 3);//ocref_clr connected to the tim_ocref_clr input

TIM3 -> AF2 |= 0 << 16;//COMP1 AS OCREF_CLR

TIM3 -> CR1 |= 1;

}

[waclawek.jan]

When OCREF_CLR is active, OCREF goes to zero, regardless of current Mode, and remains at zero until the next Update event. That means, that the respective TIMx_CHx output goes to the level given only by TIMx_CCER.CCxP polarity bit.

You have set the clear to TIM3_CH2, and TIM3_CCER.CC2P = 0, that's why the TIM3_CH2 pin goes low when the clearing event occurs.

JW

[立张.1]

When comp1 is in the stage of blanking, the output of comp1 is low, so TIM3_CH2 remains high. Only after the the stage of blanking, the output of comp1 (high), the OCREF goes to zero, then TIM3_CH2 pin goes low.

[waclawek.jan]

I'm not expert on the COMP/OCREF_CLR mechanism, but why do you think this is incorrect?

JW

[立张.1]

[立张.1]

The OCREF_CLR works only when the signal(Final comp output) is high. In blanking window, final comp output is low, so TIM3_CH2 remains its initial value high.