2022-07-21 08:00 AM - edited 2023-11-20 08:18 AM
Hi,
I am trying to init SPI1 (to just receive data qwith MISO) on nucleo G474RE without using HAL libraries.
Can you help me to assess why my code does not work ?
I can't see the clock eventhough SPI1 is enabled
void SPI1_init(){
RCC-> APB2ENR|=(1 AHB2ENR |= (1MODER &= ~(1 AFR[0] |= (1 AFR[0] |= (1 AFR[0] |= (1 CR1 |= (1 CR1 |= (1 CR1 |= (1 CR2 |=(1CR2 |= (1CR1|= (1CR1|= (1CR1&= ~(1
Solved! Go to Solution.
2022-07-22 03:19 AM
> Again, I would suggest starting with HAL to see how that does it, then base your bare-metal on that ...
I would recommend completely forget about existence of Cube/HAL, first. Then read the fine manuals, thoroughly.
The Rx-only mode is being matter of grief, especially for those who click, as it requires to know what one is doing.
JW
2022-07-21 08:38 AM
SPI1_SCK is PA5 and its MODER is set to 0b00 i.e. Input instead of 0b10 for AF.
Did not look further.
JW
2022-07-22 12:14 AM
Hi @Community member
thanks again.
I modified PA5 MODER to AF5 but there should be still something that blocks the SPI1..
I doublechecked the GPIO and SPI clock, the GPIOsettings and SPI1 settings but I cannot find what is still wrong. Can you give a look to the registers again?
The code is just about enabling this SPI1 in order to see the SPI1 clock coming out from my NUCLEOG474RE
GPIOA has clock enalbledSPI1 clock enabledPA4 PA5 and PA6 all alternate function AF5SPI registers
2022-07-22 01:18 AM
So you see still no clock on PA5 when you write into SPI1->DR, e.g. in debugger? How do the SPI registers change after that write?
I'm not sure what's the behaviour of the internal NSS node if you set SSOE as you've done. Try setting both SSM and SSI.
JW
2022-07-22 01:27 AM
I found that the only way to see the SCK line activated is to write
while (1){
SPI1->DR= something;
}
if I write directly the registers while debugging the status register is affected (RXNE bit) but I cannot see the SCK outputs (in nucleo G474RE PA5 is connected to LED 2 so it is easy to see)
Maybe this is the right behaviour of the SPI interface?
I thought that after enabling it I would have seen the SCK line activated even if I am not receving data
2022-07-22 02:13 AM
@Tommino "I thought that after enabling it I would have seen the SCK line activated even if I am not receving data"
No: the clock is generated by sending stuff out on MOSI - this is inherent to the way SPI works.
EDIT:
Correction - See below: this chip has a special 'receive-only' mode
2022-07-22 02:15 AM
@Tommino "without using HAL libraries"
I would suggest that you get it working with the HAL first - then you have a working example on which to base your bare-metal implementation.
2022-07-22 02:16 AM
Hi @Andrew Neil
But what if the uC needs only to receive data on MISO and also be the master of the communication? The uC shall generate the clock...
2022-07-22 02:17 AM
First step with HAL done
2022-07-22 02:23 AM
Ah, you're right - this one has a special 'receive-only' mode:
Again, I would suggest starting with HAL to see how that does it, then base your bare-metal on that ...